Digital Electronics & Microprocessors Test - 4 - PDF Flipbook

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GATE
EEE

DigitalElectronics
&

Microprocessors

Test-04Solutions

DIGITAL ELECTRONICS AND MICROPROCESSORS

1. Arrange the following ADCs in terms of their speed (highest to

lowest):

1) Dual slope

2) Counting

3) Successive approximation

4) Parallel comparator

Select the correct answer using the code given below:

a) 1-2-3-4

b) 2-1-3-4

c) 1-2-4-3

d) 4-3-2-1

Answer: (d)

Solution:

Type Speed Cost

Dual slope Slow Medium

Flash Very fast High

Successive approximation Medium fast Low

Sigma-Delta Slow Low

2. Memory chips of four different sizes as below are available:

1. 32K × 4

2. 32K × 16

3. 8K × 8

4. 16K × 4

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All the memory chips as mentioned in the above list are
Read/Write memory. What minimal combination of chips or
chip alone can map full address space of 8085 microprocessor?
a) 1 and 2
b) 1 only
c) 2 only
d) 4 only
Answer: (c)
Solution:
Total memory that can ve interfaced to 8085μp is 64 KB = 64 K
× 8 bits.
Now 32 K × 16 bits = 32 × 16 K bits = 512 K bits and others are
not sufficient as less than 512 K bits.
3. Consider the following Sum of products expression, F.
F = ABC + A BC + ABC + ABC + A B C
The equivalent Product of Sums expression is
a) F = (A + B + C) (A + B + C) (A + B + C)
b) F = (A +B +C) (ABC) (A + B + C)
c) F = (A + B + C) (A + B + C) (A + B + C)
d) F = (A + B +C) (A + B + C) (A + B + C)
Answer: (a)
Solution:
The sop form is F = Σm [7, 1, 5, 3, 0]; POS form = ΠM [2, 4, 6]

F = (A + B + C) (A + B + C) (A + B + C)

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4. Consider the following statements:
Data that are stored at a given address in a random access
memory are lost
1. when power goes off
2. when the data are read from the address
3. when new data are written at the address
4. because it is non-volatile memory
Which of these statements are correct?
a) 1 and 2
b) 1, 2 and 4
c) 2 and 3
d) 1 and 3
Answer: (d)
Solution:
RAM is volatile memory i.e. data are lost when power goes off.

5. The cache memory has a high speed of 40 ns and a hit ratio of
80%. The regular memory has an access time of 100 ns. The
average effective time for CPU to access memory is equal to
a) 52 ns
b) 60 ns
c) 70 ns
d) 80 ns
Answer: (a)

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Solution:
80% – Cache
20% – Regular

t = (0.2) (100) + (0.8) (40)
t = 52 ns

6. When a time varying signal has to be digitized using an ADC,
which one of the following is necessary to use before
digitization?
a) A time division multiplexer
b) A frequency division multiplexer
c) A sample and hold circuit
d) An instrumentation amplifier
Answer: (c)
Solution:
Sample and hold circuit takes sample at particular instant.

7. Assertion (A): Each memory cell of a DRAM requires
refreshing every 2, 4 or 8 ms or its data will be lost.
Reason (R): DRAM stores 1s and 0s as charges on a small
MOS capacitor which has tendency to leak off charges after a
period of time.
a) Both A and R are true and R is the correct explanation of A
b) Both A and R are true but R is not the correct explanation of
A
c) A is true but R is false
d) A is false but R is true

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Answer: (a)
Solution:
Data is stored in the MOS capacitor so if it is not refreshed
periodically it will have lost its data (as capacitor will be
discharged). So both are correct and R is also the explanation of
A.
8. The devices given below are used by microprocessor and
microcontrollers:
1. RAM
2. EPROM
3. PORTS
Which combination is available on-chip on a microcontroller?
a) 1 and 2
b) 1 and 3
c) 2 and 3
d) 1, 2 and 3
Answer: (d)
Solution:
Microcontroller has
1. ROM
2. RAM
3. Ports
4. Timers
5. Interrupt controls
6. A/D converters

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7. CPU
9. The complete set of only those Logic Gates designated as

Universal gates is
a) NOT, OR and AND Gates
b) XNOR, NOR and NAND Gates
c) NOR and NAND Gates
d) XOR, NOR and NAND Gates
Answer: (c)
10. To address the full memory space of an Intel 8085
microprocessor four RAMS of different sizes are available.
1. 8 K x 8
2. 16 K x 4
3. 32 K x 4
4. 32 K x 16
What minimal combination of chip (s) will serve the purpose?
a) 1, 2, 3 and 4
b) 2
c) 3
d) 4
Answer: (d)
Solution:
8085: has 16-bit address total memory that can be interfaced

= 216 × 8 = 64 K-byte
= 64 × 8 K-bits
= 512 K-bits

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In option 4,
32K × 16 = 32 × 16 K-bits
= 512 K-bits
So, statement 4 is correct

11. Which one of the following statements is correct?
In comparison with static RAM memory, the dynamic RAM
memory has
a) Lower bit density and higher power consumption.
b) Higher bit density and higher power consumption.
c) Lower bit density and lower power consumption.
d) Higher bit density and lower power consumption.
Answer: (b)
Solution:
• DRAM needs to be refreshed periodically which requires
more power.
• DRAM requires lesser transistor than SRAM, so bit density is
higher.

12. Statement (I): Partial memory address decoding can result in
simplified decoding logic.
Statement (II): Partial decoding causes many-to-one mapping
of addresses to memory location.
a) Both Statement (I) and Statement (II) are individually true
and Statement (II) is the correct explanation of Statement (I).

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b) Both Statement (I) and Statement (II) are individually true
but Statement (II) is not the correct explanation of Statement
(I).

c) Statement (I) is true but Statement (II) is false.
d) Statement (I) is false but Statement (II) is true.
Answer: (b)
13. The address lines A15 to A9 of a microprocessor with 64 k
memory capacity are connected to the chip select line of a 512 x
8 EPROM through an AND gate. Its memory map ranges from
0000 to
a) 00FF
b) 03FF
c) 02FF
d) 01FF
Answer: (d)
Solution:

14. The reference bit is used for the purpose of
a) Implementing LRU page replacement algorithm
b) Implementing NRU (Not Recently used) algorithm
c) To check if the page table entry is in cache memory
d) Check if the page has been written into recently
Answer: (b)

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15. Match List-I (Application) with List-II (Implementation
platform) and select the correct answer using the codes given
below the lists:
List-I
A. Control logic for a toy that is sold in large quantities
B. Control logic for a microprocessor that is still in the
development stage
C. Store files in an embedded system
D. Control logic for a project to be demonstrated occasionally
List – II
1. EPROM
2. PROM
3. ROM
4. EEPROM
Codes:
ABC D
a) 2 1 4 3
b) 3 1 4 2
c) 2 4 1 3
d) 3 4 1 2
Answer: (d)
Solution:
A – Toys – ROM (Not programmable); B – Development stage
– Electrical erasable ROM; C – Embedded system – EPROM
D – Occasional demo - PROM

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16. Which of the following are required for a multimedia PC?
1. CD-ROM drive, speaker and sound card.
2. Modem and network card.
3. Hardware needed to display videos and animation.
4. Software needed to display videos and animation.
Select the correct answer using the codes given below:
Codes:
a) 1, 2 and 3
b) 1, 2, 3 and 4
c) 1, 2 and 4
d) 1, 3 and 4
Answer: (d)

17. How many and which types of machines cycles are needed to
execute PUSH PSW by an Intel 0885 A microprocessor?
a) 2, Fetch and Memory write
b) 3, Fetch and 2 Memory write
c) 3, Fetch and 3 Memory write
d) 3, Fetch, Memory read and Memory write
Answer: (b)

18. In an 8085 microprocessor, after the execution of XRA A
instruction
a) the carry flag is set
b) the accumulator contain FFH
c) the Zero flag is set
d) the accumulator contents are shifted left by one bit

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Answer: (c)
Solution:
XRA A' instruction execution resets contents of accumulator
and hence sets zero flag.
19. Which of the following methods could be used for I/O
operation in an 8085 microprocessor?
1. Hand Shaking
2. Interrupting
3. Direct Memory Access
Select the correct answer using the codes given below:
a) 1 and 2
b) 1 and 3
c) 2 and 3
d) 1, 2 and 3
Answer: (d)
Solution:
Interrupt is interrupting the normal execution of a program to
perform some specific task. It is a dynamic call of service sub-
routing through external hardware. It is an asynchronous process
of communication with the microprocessor initiated by an
external peripheral.
Handshaking - MPU and Peripheral (I/O) operates at different
speeds. Therefore signals are exchanged prior to data transfer
between fast responding MPU and slow peripheral such as
printers. This is called handshaking.

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DMA – Data transfer between system memory and outside
peripheral like disc.
20. Which one of the following statement for Intel 8085 is correct?
a) Program counter (PC) specifies the address of the instruction

last.
b) PC specifies the address of the instruction being executed.
c) PC specifies the address of the instruction to be executed.
d) PC specifies the number of instructions executed so for.
Answer: (c)
21. In the 2's complement Adder-Subtractor given the numbers X

= 00011000 and Y = 11110000. They stand respectively for
a) 24 and 240
b) 18 and 15
c) 6 and –15
d) 24 and –16
Answer: (d)
22. In a multiprocessor configuration, two co-processors are
connected to the host 8086 processor. The two co-processor
instruction sets
a) must be the same
b) may be overlap
c) must be disjoint
d) must be the same as that of the host
Answer: (d)

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23. Which of the following addressing modes imply that the
operand is stored separately in the main memory?
1. Indirect
2. Immediate
3. Indexed
Select the correct answer using the code given below:
a) 1, 2 and 3
b) 1 and 2
c) 2 and 3
d) 1 and 3
Answer: (d)
Solution:
In immediate addressing mode operand is specified in the
instruction itself.
e.g. LXI B, 0088 H
0088 H is stored in BC register pair.
In indexed addressing mode, the contents of index register are
added with a constant value to get the address of the operand.

24. Four jobs to be executed on a single processor system arrive at
time 0+ in the order A, B, D, D. Their burst CPU time
requirements are 4, 1, 8, 1, time units respectively. The
completion time of a under round robin scheduling with time
slice of one time unit is
a) 10
b) 4

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c) 8
d) 9
Answer: (d)
25. When used with I/O devices, the term intelligent implies
a) a colour output capability
b) speech processing capability
c) high speed printing capability
d) features to support offline and online tasks
Answer: (d)
26. The 8085 microprocessor responds to the presence of an
interrupt
a) as soon as the TRAP pin becomes 'high'.
b) by checking the TRAP pin for 'high' status at the end of each

instruction fetch.
c) by checking the TRAP pin for 'high' status at the end of

execution of each instruction.
d) by checking the TEAP pin for 'high' status at regular interval.
Answer: (a)
Solution:
TRAP is a non-maskable interrupt. When signal on TRAP PIN
is high, the microprocessor stops execution of the current
instruction being executed and immediately calls the sub-routine
stored at (0024)H.

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27. What is the minimum number of operations required in a
microprocessor with 8 data pins to read a 32-bit word?
a) 1
b) 2
c) 4
d) 8
Answer: (c)

28. Consider the following circuit which uses a 2-to-1 multiplexer
as shown in the figure below. The Boolean expression for output
F in terms of A and B is

a) ⨁
b) +
c) +
d) ⨁
Answer: (d)
Solution:

F = S�I0 + SI1
= B�A� + BA

= A⨀B
= � � �⨁��� �

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29. The three buses associated with three-bus system are I/O bus,
memory bus and
a) address bus
b) unibus
c) direct memory access bus
d) data bus
Answer: (c)

30. Assertion (A): When large amount of data is to be printed out
from the memory of a computer, DMA is used.
Reason (R): DMA avoids using the CPU thus allowing the CPU
to attend to another job.
a) Both A and R are true, and R is the correct explanation of A.
b) Both A and R are true, but R is not a correct explanation of
A.
c) A is true, but R is false.
d) A is false but R is true.
Answer: (a)
Solution:
DMA avoids the use of CPU/MPU in data transfer as MPU/CPU
slows down the data transfer. So to transfer large data i.e.
transfer from memory to disc or memory to printer, DMA is
used.

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