Computer Organization Test - 4 - PDF Flipbook
Computer Organization Test - 4
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GATE
CSE
Computer
Organization
Test-04Solutions
COMPUTER ORGANIZATION
1. Which of the following transmission media is used in Bluetooth
Technology?
a) Radio links
b) Microwave links
c) VSAT Communication
d) Fibber-optic
Answer: (a)
Solution:
Radio links protocol is an automatic repeat request fragmentation
protocol used over a wireless air interface most wireless air
interface are tuned to provide 1% packet loss and most vocoders
are mutually turned to sacrificed very little voice quality at 1%
packet loss
A microwave link is a communications system that uses a beam
of radio waves in the microwave frequency range to transmit
information between two fixed locations on the earth
VSAT is a satellite communications system that server home and
business users
A fibre optical cable consists of a bundle of glass threads, each of
which is capable of transmitting message modulated onto light
waves
2. In 2's complement addition, the overflow
a) is flagged whenever there is carry from sign bit addition
b) cannot occur when a +ve value is added to a -ve value
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c) is flagged when it carries from sign bit & previous bit match
d) none of the above
Answer: (b)
Solution:
Addition of one positive and one negative number gives
subtraction operation so there is no overflow.
3. A main memory unit with a capacity of 4 megabytes is built
using 1M x 1-bit DRAM chips. Each DRAM chip has 1K rows
of cells with 1K cells in each row. The time taken for a single
refresh operation is 100 nanoseconds. The time required to
perform one refresh operation on all the cells in the memory unit
is
a) 100 nanoseconds
b) 100*210 nanoseconds
c) 100*220 nanoseconds
d) 3200*220 nanoseconds
Answer: (b)
Solution:
For one refresh operation 1 row gets refresh in all chips. So total
number of refresh operations needed is total number of rows in
memory system.
4. Refer the points as listed below:
i. What are the operator precedence rules?
ii. What are the operator associativity rules?
iii. What is the order of operand evaluation?
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iv. Are there restrictions on operand evaluation side effects?
Which of the above must be considered as primary design issues
for arithmetic expressions?
a) (i), (ii) and (iii)
b) (i), (iii) and (iv)
c) (i), (ii)and (iv)
d) (i), (ii), (iii)and (iv)
Answer: (d)
Solution:
Arithmetic expressions: unary, binary ternary operators meaning
an operator can have one two or three operand respectively
Design issue include:
• What are the operator precedence rule?
• What are the operator associativity rule?
• What is the order of operand evaluation?
• Are there restrictions on operand evolution side effects?
• Does the language allow user-defined –operator overloading?
• The type mixing is allowed in expressions?
5. Consider the following code sequence having five instructions 11
to 15. Each of these instructions has the following format.
OP Ri, Rj, Rk
Where operation OP is performed on contents of registers Rj and
Rk and the result is stored in register Ri.
I1: ADD R1, R2, R3 I2: MUL R7, R1, R3
I3: SUB R4, R1, R5 I4:ADD R3, R2, R4
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I5: MUL R7, R8, R9
Consider the following three statements
S1: there is an anti-dependency between instruction I2 and I5
S2: there is anti-dependence between instruction I2 and I4
S3: within an instruction pipeline anti-dependence always
created one or more stalls
Which one of above statements is/are correct?
a) Only Sl is true
b) Only S2 is true
c) Only S1 and S3 are true
d) Only S2 and S3 are true
Answer: (b)
Solution:
It is also known as W.A.R Hazard,. Anti-dependence Hazard
creates Hazard (i.e. needs stall) when a lower latency instruction
is completed before a longer latency instruction that appears
earlier in the program only BUT NOT ALWAYS.
6. Which of the following are true in a pipelined processor?
• Bypassing can handle all RAW hazards.
• Register renaming cart eliminate all register carried WAR
hazards.
• Control hazard penalties can be eliminated by dynamic
branch Prediction.
a) 1 and 2 only
b) 1 and 3 only
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c) 2 and 3 only
d) 1, 2 and 3
Answer: (c)
Solution:
Bypassing cannot handle all RAW hazards. Register renaming
can eliminate all register carried WAR hazards. Control hazard
penalties can be eliminated by dynamic branch prediction.
7. Match the following:
List-I
A. Tablet, Joystick
B. Light Pen, Touch Screen
C. Locator, Keyboard
D. Data Globe, Sonic Pen
List-II
1. Continuous devices
2. Direct devices
3. Logical devices
4. 3D interaction devices
Codes:
AB CD
a) 2 1 4 3
b) 1 4 3 2
c) 1 2 3 4
d) 4 3 2 1
Answer: (c)
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Solution:
Table, joystick are continuous devices since we cannot left out
hand during their operation light pen touch screen are direct
devices since we can input/touch devices since we can
input/touch directly
Keyboard, locator are logical devices
Data globe, sonic pen are 3D interaction devices
8. Increasing the RAM of a computer typically improves
performance because :
a) Virtual memory increases
b) Larger RAMs are faster
c) Fewer page faults occur'
d) Fewer segmentation faults occur
Answer: (c)
Solution:
Increasing the RAM means increasing the main memory,
through which more pages can be accommodated. So fewer page
faults occur
9. The LAPB frame structure and the frame structure of SDLC are:
a) Opposite
b) identical
c) Reversed
d) Non-identical
Answer: (b)
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Solution:
When one-dimensional character array of unspecified is assigned
an initial value “%” (null) is added at the end of the string.
10. Consider a system with 2 level cache. Access times of Level 1
cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500
ns, respectively. The hit rates of Level 1 and Level 2 caches are
0.8 and 0.9, respectively. What is the average access time of the
system ignoring the search time within the cache?
a) 13.0
b) 12.8
c) 12.6
d) 12.4
Answer: (c)
Solution:
Assuming hierarchical access: = H1T1 + (1 – H1) H1 (T1 + T2) +
(1 – H1) (1 – H2) (T1 + T2 + T1)
= 0.8 × 1 + (0.2) (0.9) (11) + (0.2 × 0.1) (511) = 13
Assuming simultaneous access: = H1T1 + (1 – H1) H2 T2 + (1 –
H1) (1 – H2) T3
= 0.8 × 1 + (0.2) (0.9) ×10 + (0.2) (0.1) × 500 = 12.6 nsec
Both are present in options.
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11. Which of the following is/are true of the auto increment
addressing mode?
1. It is useful in creating self-relocating code
2. If it is included in an Instruction Set Architecture, then an
additional ALU is required for effective address calculation
3. The amount of increment depends on the size of the data item
accessed.
a) l only
b) 2 only
c) 3 only
d) 2 and 3 only
Answer: (c)
Solution:
In auto-increment addressing, mode the amount of increment
depends on the size of the data item accessed.
12. Consider a pipelined processor with the following four stages:
IF: instruction Fetch
ID: instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete
the operation. The ADD and SUB instructions need 1 clock
cycle and the MUL instruction needs 3 clock cycles in the EX
stage. Operand forwarding is used in the pipelined processor.
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What is the number of clock cycles taken to complete the
following sequence of instructions?
ADD R2, R1, R0 R2 ←R1+R0
MUL R4, R3, R2 R4 ← R3*R2
SUB R6, R5, R4 R6 ← R5 – R4
a) 7
b) 8
c) 10
d) 14
Answer: (b)
Solution:
Pipelines processor has 4 stages IF, ID, EX, WB
Clock Cycles Instruction
1 ADD
1 SUB
3 MUL
13. Assume that the memory is word addressable. After the
execution of this program, the content of memory location 2010
is
a) 100
b) 101
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c) 102
d) 110
Answer: (a)
Solution:
As the memory locations are incremented 10 times from 2000 to
2009, when the loop is terminated R3 consists of 2010, whose
value will be 100(previous value) only.
14. Which of the following addresses is used to deliver a message to
the correct application program running on a host?
a) Port
b) IP
c) Logical
d) Physical
Answer: (a)
Solution:
A port number is a way to identity a specific process to which an
internet or other network message is to forwarded when it arrives
at a server for the TCP abd UDP, a point number is a 16 bit
integer that is put in the header appended to a message unit
Specific port numbers are often used to identify specific services
15. For computers based on three-address instruction formats, each
address field can be used to specify which of the following.
S1: A memory operand
S2: A processor register
S3: An implied accumulator registers.
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a) Either S1 or S2
b) Either S2 or S3
c) Only S2 and S3
d) All of S1, S2 & S3
Answer: (a)
Solution:
Address field in the instruction is used to specify Memory
Address or one of the processor Register Address.
For example, to specify R5 in a processor which is having 16
Register from R0 to R15, it's Address field is '0101', and for
implied Register; no address is specified in the instruction.
16. Which one of the following is true for asymmetric key
cryptography?
a) Private key is kept by the receiver and public key is
announced to the Public.
b) Public key is kept by the receiver and private key is
announced to the Public.
c) Both private key and public key are kept by the receiver.
d) Both private key and public key are announced to the Public
Answer: (a)
Solution:
In asymmetric or public- key cryptography there are two keys a
private key and public key the private key is kept by recover the
public key is announced to the public, the public key that is used
for encryption is different from the private key that is used for
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decryption the public key is available to the public; the private
kay is available only to an individual
17. Given the following binary number in 32-bit (single precision)
IEEE-754 format: 00111110011011010000000000000000 The
decimal value closest to this floating point number is
a) 1.45 × 10-1
b) 1.45 × 10-1
c) 2.27 × 10-l
d) 2.27 × 101
Answer: (c)
Solution:
00 11111 00 110 110 1000…0
S = , E = 01111100,
M = 11011010…0
Expressions value = (-1)S × 1.M × 2E-127
= (-1) × 1.110110102 ×2-3
= 1.8510 × 1
8
= 0.23
= 2.3 × 10-1
18. The n-bit fixed-point representation of an unsigned real number
X uses f bits for the fraction part. Let i = n – f. The range of
decimal values for X in this representation is
a) 2-f to 2i
b) 2-fto (2i - 2-f)
c) 0 to 2i
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d) 0 to (2i - 2-f)
Answer: (d)
Solution:
Real number size is n bits
Type of data is unsigned
Fraction part size = f bits
Integer part size = (n – f) bits
Range of the decimal values for
only integer part is (0 to 2i – 1)
Range of the Decimal value for only
Fractional part is (0 to (1 – 2–f))
Range of the real number is 0 to (2i – 1 + 1 – 2-f)
= 0 to (2i – 2-f)
19. A device with data transfer rate l0 KB/sec is connected to a CPU.
Data is transferred byte-wise. Let the interrupt overhead be 4
psec. The byte transfer time between the device interface register
and CPU or memory is negligible. What is the minimum
performance gain of operating the device under interrupt mode
over operating it under program controlled mode?
a) 15
b) 25
c) 35
d) 45
Answer: (b)
Solution:
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10 KBPS = 10KB is transferred in 1 sec = 104 B
1 byte takes = 0.1 ms = 100 s
Minimum waiting time needed is 100 s for system
Gain = 100
4
= 25
20. How many tokens will be generated by the scanner for the
following statement?
X = x*(a + b)-5;
a) 12
b) 11
c) 10
d) 07
Answer: (a)
Solution:
Given expression is:
X = x*(a + b) –5;
Total numbers of tokens that will be generated are for:
(1) x (2) =
(3) x (4) *
(5) c (6) a
(7) + (8) b
(9) ) (10) -
(11) 5 (12) =;
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21. Start and stop bits do not contain ‘information’ but these are used
in serial communication for
a) Error detection
b) Error correction
c) Synchronization
d) Slowing down the communication
Answer: (c)
Solution:
Start & stop bits are used for synchronization
22. Consider a machine with a byte addressable main memory of 220
bytes, block size of 16 bytes and a direct mapped cache having
212 cache lines. Let the addresses of two consecutive byes in
main memory be (E201F)16 and (E2020)16. What are the tag and
cache line address (in hex) for main memory address (E20 I F)16?
a) E, 201
b) F, 201
c) E, E20
d) 2, 01F
Answer: (a)
Solution:
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23. In which addressing mode, the effective address of the operand
is generated by adding a constant value to the contents of
register?
a) absolute mode
b) immediate mode
c) indirect mode
d) index mode
Answers: (d)
Solution:
In index addressing mode address of the operand is abtained by
adding to the contents of the general register (called index
register) a constant value the number of the index register and the
constant value are included in the instruction code index mode is
used to access an array whose elements are in successive
memorry locations.
The effective address for an absolute instruction address is the
address parameters itself with no modifications
Immediate addfressing mode does not have an effective address
and is not considered to be an addressing mode on some
computers
24. The correct matching for the following pairs is
List - I
a. DMA I/O
b. Cache
c. Interrupt I/O
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d. Condition code Register
List - II
(1) High speed RAM
(2) Disk
(3) Printer
(4) ALU
Codes:
a) a – 4, b – 3, c – 1, d – 2
b) a – 2, b – 1, c – 3, d – 4
c) a – 4, b – 3, c – 2, d – 1
d) a – 2, b – 3, c – 4, d – 1
Answer: (b)
25. Which of the following is not valid with reference to Message
Passing interface (MPI)?
a) MPI can run on any hardware platform.
b) The programming model is a distributed memory model.
c) All parallelism is implicit.
d) MPI-Comm-Size returns the total number of MPI processes in
specified communication.
Answer: (c)
Solution:
Message passing interface is a standardized and portable
message passing system designed by group of researchers from
academic and industry to function on a acid variety of parallel
computing architectures all parallel computing architectures
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26. Which of the following special cases does not require
reformulation of the problem in order to obtain a solution?
a) Alternate optimality
b) infeasibility
c) Unboundedness
d) All of the above
Answer: (a)
Solution:
An alternative optional solution which is when a linear/ integer
programming problem has more than one optional solution
Typically an optimal solution is a solution to a problem which
satisfies the set of constraints of the problem which is to
maximum or minimize
Alternate optimality does not require reformulation of the
problem in order to obtain a solution and infeasibility and
unboundedness require reformulation of the problem
27. More than one word are put in one cache block to
a) Exploit the temporal locality of reference in a program
b) Exploit the spatial locality of reference in a program
c) Reduce the miss Penalty
d) None of the above
Answer: (b)
Solution:
Exploit the spatial locality of reference in a program.
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28. For a pipelined CPU with a single ALU, consider the following
situations
1.The j + 1 instruction uses the result of the j-th instruction as an
operand
2.The execution of a conditional jump instruction
3.The j-th and j + 1 instruction require the ALU at the same time
Which of the above can cause a hazard?
a) 1 and 2 only
b) 2 and 3 only
c) 3 only
d) All the three
Answer: (d)
Solution:
The j+1 instruction uses the result of the ith instruction a san
operand, comes under data dependency and it causes data hazard
The execution of a conditional jump instruction comes under
conditional dependency and it causes control hazard
The jth and j + 1 instruction required the ALU at the time comes
under structural hazard.
29. Match the following with respect to the Mobile Computing
Architecture.
List: I
A. Downlink control
B. Radio communication data rate
C. The average duration of users stays in cell
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D. FDDI bandwidth
List: II
1. 100Mbp
2. Residency latency (RL)
3. Sending data from a BS to MD
4. 2-Mbps
Codes:
AB C D
a) 2 1 4 3
b) 3 4 2 1
c) 4 1 2 1
d) 4 3 1 2
Answer: (b)
Solution:
The base station subsystem is the section of a traditional cellular-
telephone network which is responsible for handling traffic and
signalling- switching subsystem so, this statement indicating
downlink control is used to sending data from a BS to MD
Users are highly mobile and randomly enter and exit from cells
there is a parameter called residence latency, which characterizes
the average duration of a user’s stg in the cell
The FDDI (Fibber distributed data interface specifies 100 mbps
token passing dual-ring LAN using fibre-optic cable.
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30. In the IEEE floating point representation the hexadecimal value 0
x 00000000 corresponds to
a) the normalized value 2-127
b) the normalized value 2-126
c) the normalized value +0
d) the special value +0
Answer: (d)
Solution:
If mantissa and exponent have all zeros then it is used to
represent + 0.
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