Computer Organization Test - 3 - PDF Flipbook
Computer Organization Test - 3
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GATE
CSE
Computer
Organization
Test-03Solutions
COMPUTER ORGANIZATION
1. The concept of pipelining is most effective in improving
performance if the tasks being performed in different stages:
a) require different amount of time
b) require about the same amount of time
c) Require different amount of time with different difference
between any two tasks being Sam
d) require different amount with time difference between any
two tasks being different
Answer: (b)
Solution:
If different stages require different amounts of time, the clock
period must be allowing the longest task to be completed a unit
that completes its task early is idle for the remainder of the clock
period Hence, pipe line is most efficient in improving
performance if the tasks being performance in different stages
required same amount of time
2. Which of the following device should get highest priority in
assigning interrupts?
a) Hard disk
b) Printer
c) Keyboard
d) Floppy disk
Answer: (a)
1
Solution:
CPU gives highest priority for high speed devices and least
priority for low speed devices. Hard disk has higher priority
than others because it is fastest secondary memory.
3. A fast wide SCSI – II disk drive spins at 7200 RPM, has a sector
size of 512 bytes, and holds 160 sectors per track. Estimate the
sustained transfer rate of this drive.
a) 576000 Kilobytes / sec
b) 9600 Kilobytes / sec
c) 4800 Kilobytes / sec
d) 19200 Kilobytes / sec
Answer: (b)
Solution:
Size of track = 160 × 512B
Rotation per minute = 7200
1 revolution will take time = 1120sec
In 1sec, it will red = 160×512 byte
1/120
= 160×512×120 = 9600 KBps
4. How many 8-bit characters can be transmitted per second over a
9600 baud serial communication link using asynchronous mode
of transmission with one start bit & Eight data bits, two stop
bits, and one parity bit?
a) 60
b) 800
2
c) 876
d) 1200
Answer: (b)
Solution:
Character = 1 + 8 + 2 + 1 = 12
CPS = 9600 = 800
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5. Consider a 33MHz cpu based system. What is the number of
wait states required if it is interfaced with a 60ns memory?
Assume a maximum of 10ns delay for additional circuitry like
buffering and decoding.
a) 0
b) 1
c) 2
d) 3
Answer: (d)
Solution:
Total memory access delay = Memory time + additional delay =
(16 +10) = 70 ns
CPU time = 1/Frequency = 1/33 MHZ
= 30.30 ns
So, number of cycles (i.e., wait state) = �307.030�
= 3 wait state
Note: A wait state is the delay experience by processor when
accessing another device with slower speed i.e cycle
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6. A ROM is used to store a truth table for a binary multiplier unit
that will multiply two 4 bit numbers. The size of the ROM
(number of words x number of bits) that is required to
accommodate the truth table is M words x N bits. Write the
values of M and N.
Solution:
M = 256 and N = 8
7. Consider the following reservation table for a pipeline having
three stages S1, S2, and S3.
The minimum average latency (MAL) is _____.
Answer: 3
8. The decision tree classifier is a widely used technique
for_______
a) Classification
b) Association
c) Partition
d) Clustering
Answer: (a)
Solution:
Decision tree classification is a simple and widely used
classification technique it applies a straightforward idea to solve
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the classification problem, Decision tree classifier poses a series
of carefully crafted question about the attributes of the test
record. Each time it retrieves an answer a follow-up question is
asked until a conclusion about the class label of the record is
reached.
9. In an instruction execution pipeline, the earliest that the data
TLB (Translation Look Aside Buffer) can be accessed is
a) Before effective address calculation has started
b) During effective address calculation
c) After effective address calculation has completed
d) After data cache lookup has completed
Answer: (b)
10. In a vectored interrupt
a) The branch address is assigned to a fixed location in memory
b) The interrupting source supplies the branch information to the
processor through an interrupt vector.
c) The branch address is obtained from a register in the
processor.
d) None of these
Answer: (b)
Solution:
For vectored hardware interrupt, the _interrupting device
supplies the respective address with additional hardware.
5
11. If a program P calls two subprograms P1 and P2 and P1 can fail
50% of the time and P2 can fail 40% of the time, what is the
failure rate of program P?
a) 50%
b) 60%
c) 70%
d) 10%
Answer: (c)
Solution:
Program ‘p’ fails when either P1 fails or P2 fails
Failure rate of P = (Failure of P1) + (Failure of P2) – (Failure of
P1 ∩ Failure of P2) = 50 + 40 − 50 × 40 = 90 − 20 = 70
100 100 100 100 100 100 100
12. Which of the following addressing modes are suitable for
program relocation at run time?
1. Absolute addressing
2. Based addressing
3. Relative addressing
4. Indirect addressing
a) 1 and 4
b) 1 and 2
c) 2 and 3
d) 1,2 and 4
Answer: (c)
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Solution:
Absolute Addressing & indirect addressing is not suitable for
indirection. Base addressing mode & relative addressing mode
are suitable for program relocation at run time due to following
reasons. In relative addressing mode the operand field contains a
relative address, which is also called an offset or displacement
D. In base addressing mode the operand fie1d contains the
displacement. The absolute address is calculated as follows:
A = R + D, Where R is a register mostly a Program Counter for
relative addressing and Base register for base addressing mode.
By changing contents of R, the processor can change the
absolute address referred to a new block of instructions. This
address modification allows the processor to relocate the entire
new block from one region of main memory to another without
invalidating the addresses.
13. identify the incorrect statement:
a) The internet has evolved into phenomenally successful e-corn
Merced engine
b) Business i: synonymous with +commerce
c) The e-commerce model B2C did not begin with billboard
ware
d) The e-commerce model G2C began with Billboard ware
Answer: (b)
7
Solution:
E-commerce is narrows concept and restricted to buying and
selling e-business is a border concept that involves market
surveying, supply chain and logistics management and using
data mining. it is used in the context of B2B transition
E-business can involve the use of internet intranet or extranet
14. In serial data transmission, every bite of data is padded with a '0'
in the beginning and one or two 1's at the end of byte because
a) Receiver is to be synchronized for byte reception
b) Receiver recovers lost 0's & l's from these padded bits
c) Padded bits are useful in parity computation
d) None of the above
Answer: (a)
15. The instruction “call Rn, sub" is a two-word instruction.
Assuming that PC is incremented during the fetch cycle of the
first word of the instruction, its register transfer interpretation is
Rn ⟸ PC + 1;
PC ⟸ M[PC];
The minimum number of CPU clock cycles needed during the
execution cycle of this instruction is:
a) 2
b) 3
c) 4
d) 5
Answer: (b)
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Solution:
Execution cycle: clock cycle
1- PC +1 to Rn
2- Clock cycle 2&3 – M[PC] to PC
3- 3 clock cycles are required
16. Assume that each character code consists of 8 bits. The number
of characters that can be transmitted per second through an
asynchronous serial line at 2400 baud, rate, and with two stop
bits, is:
a) 109
b) 216
c) 218
d) 240
Answer: (c)
Solution:
Baud rate is 2400;
One character needs 8 bits + 2 stop bits and one start bit is
compulsory,
So, 11 bits are needed = 2400 = 218
11
17. Which one of the following is true for a CPU having a single
interrupt request line and single interrupt grant line?
a) Neither vectored interrupt nor multiple interrupting devices
are possible
b) Vectored interrupts are not possible but multiple interrupting
devices are possible
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c) Vectored interrupts and multiple interrupting devices are both
possible
d) Vectored interrupt is possible but multiple interrupting
devices are not possible
Answer: (b)
Solution:
In single line interrupt system contains a single interrupt request
line and an interrupt grant line. In this system it may be possible
for more than one I/O device request interrupt at the same time.
By using 8259 IC it is possible to connect more number of IO
devices. So in single interrupt system vectored interrupts are not
possible but multiple interrupting devices are possible.
18. The syntax of capturing events method for document object is
a) Capture Events ()
b) Capture Events (Orgs event Type)
c) Capture Events (event Type)
d) Capture Events (event Val)
Answer: (c)
Solution:
Capture events (Event Type) method instructs the window to
capture all events of a particular type.
10
19. Consider the C struct defined below:
struct data
{
Int marks [100];
Char grade;
Int number;
};
Struct data student;
The base address of students is available in register R1. The
field student grade can be accessed efficiently using
a) Post-increment addressing mode, (R1)+
b) Pre-decrement addressing mode, -(R1)
c) Register direct addressing mode, R1
d) Index addressing mode. X(R1), where X is an offset
represented in 2's complement 16-bit representation.
Answer: (d)
Solution:
While finding the grade of the student, it adds the displacement
value to the Roll number of the student.
Hence, it is Index Addressing mode.
20. In which way(s) a microprocessor for assembly language can be
implemented?
a) independent two-pass processor
b) independent one-pass processor
c) Expand macro calls and substitute arguments
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d) all of the above
Answer: (d)
Solution:
All given options are true
21. In a k-way set associative cache, the cache is divided into v sets,
each of which consists of k lines. The lines of a set are placed in
sequence one after another. The lines in set s are sequenced
before the lines in set (s+1). The main memory blocks are
numbered 0 onwards. The main memory block numbered j must
be mapped to any one of the cache lines from
a) (j mod v)*k to (j mod v)*k + (k ‒ 1)
b) (j mod v) to (j mod v) + (k ‒ 1)
c) (j mod k) to (j mod k) + (v ‒ 1)
d) (j mod k)*v to ( mod k)*v + (v ‒ 1)
Answer: (a)
Solution:
Position of M.M set in the cache is (M.M block no.) Mod(Total
number of cache sets) As the lines in the set are placed in
sequence, we can have the cache blocks(lines) from 0 to (k -1)
in each set
Number of sets = V, M.M block no = J
So 1st line of cache = (j mod v) × K
Last line of the cache = (j mod v) × K + (k – 1)
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22. Which of the following is/are not true?
S1: The set of negative integers is countable
S2: The set of integers that are multiples of 7 is countable.
S3: The set of even integers is countable.
S4: The set of real numbers between O and l/2 is countable.
a) S1 and S3
b) S2 and S4
c) S2 only
d) S4 only
Answer: (d)
Solution:
A set is countable if, (S1) it is finite (S2) it has the same
candidate (size) as the set of natural number
Equivalent a set is countable if it has the same cardinality as the
subset of the set of natural number otherwise it is uncountable
The set of real numbers between 0 and ½ is uncountable infinite
The set of all integers are countable
23. Consider a disk pack with 16 surfaces, I28 tracks per surface
and 256 sectors per track. 512 bytes of data are stored in a bit
serial manner in a sector. The capacity of the disk pack and the
number of bits required to specify a particular sector in the disk
are respectively
a) 256 Mbyte, 19 bits
b) 256 Mbyte, 28 bits
c) 512 Mbyte, 20 bits
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d) 64 Gbyte, 28 bits
Answer: (a)
Solution:
H = 24, T = 27, S = 28 and B = 29
Capability of disk pack = h × T × S × B
= 24 ×27 × 28× 29 = 228B = 256MB
For addressing a particular sector in disk Address format is
< Surface offset, Track offset, Sector Offset >
< 4, 7, 8 > = 19 bits
24. Register renaming is done in pipelined processors
a) as an alternative to register allocation at compile time
b) for efficient access to function parameters and local variables
c) to handle certain kinds of hazards
d) as part of address translation
Answer: (c)
Solution:
Register renaming is done is pipelined processors to handle
certain kind of hazards i.e., RAW hazard, WAR hazard and
WAW hazard.
25. Comparing the time T1 taken for a single instruction on a
pipelined CPU with time T2 taken on a non-pipelined but
identical CPU, we can say that
a) T1 ≤ T2
b) T1 ≥ T2
c) T1 ≤ T2
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d) T1 is T2 plus the time taken for one instruction fetch cycle
Answer: (b)
Solution:
In pipelined CPU, there will be buffer register delays. So for
executing one instruction non-pipelined CPU takes less time
compared to pipelined CPU
26. Which of the following is / are restriction(s) rn classless
addressing?
a) The number of addresses needs to be a power of 2.
b) The mask needs to be included in the address to define the
block.
c) The starting address must be divisible by the number of
addresses in the book
d) all of the above
Answer: (d)
Solution:
There are three restrictions in classless addressing:
i. the number of address needs be a power of 2
ii. the mask needs to be included in the address to definite the
block
iii. The starting address must be divisible by the number of
addressing in the block
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27. Which of the following color models are defined with three
primary colours?
a) RGB and HSV color models
b) CMY and HSV color models
c) HSV and HLS color models
d) RGB and CMY color models
Answer: (d)
Solution:
RGB and its subset CMY from the most basic and well-known
color model, this model bears closest resemblance to how we
perceive color, it subtractive colours
28. A computer handles several interrupt sources of which of the
following are relevant for this question.
• Interrupt from CPU temperature sensor (raises interrupt if
CPU temperature is too high)
• Interrupt from Mouse (raises interrupt if the mouse is
moved or a button is pressed)
• Interrupt from Keyboard (raises interrupt when a key is
pressed or released)
• Interrupt from Hard Disk (raises interrupt when a disk read
is completed)
Which one of these will be handled at the HIGHEST priority?
a) Interrupt from Hard Disk
b) Interrupt from Mouse
c) Interrupt from Keyboard
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d) Interrupt from CPU temperature sensor
Answer: (d)
Solution:
CPU first takes care about its temperature.
29. Which is the correct definition of a valid process transition in an
operating system?
a) Wake up: Ready → Running
b) Dispatch: Ready → Running
c) Block: Ready → Running
d) Timer run out: Ready → Blocked
Answer: (b)
Solution:
There are 6 possible valid transitions among 5 states
1. Block( process name)
Running → Ready
2. Time-Run-Out(process name);
Running → Ready
3. Dispatch (process name):
Ready → Running
4. Wake up (process name);
Blocked → Ready
5. Admitted (process name);
New → Ready
6. Exit (process name);
Running → Terminated
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30. The program and adjusting the code and data in the program to
reflect the assigned addresses is called_____.
a) Symbol resolution
b) Parsing
c) Assembly
d) Relocation
Answer: (d)
Solution:
Relocation is the process of assigning load addresses to various
parts of a program and adjusting the code and data in the
program to reflect the assigned addresses
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