Digital Logic Design Test - 5 - PDF Flipbook
Digital Logic Design Test - 5
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GATE
CSE
DigitalLogic
Design
Test-05Solutions
DIGITAL LOGIC DESIGN
1. How many 2-input multiplexers are required to construct a 210-
input multiplexer?
a) 1023
b) 31
c) 10
d) 127
Answer: (a)
Solution:
At the first, there will be 512 MUX at second level, there will be
256 MUX, at third level 128 MUX will be there continuous so
till 1 MUX ie = s required
Total required = 512 + 256 + 128 + 64 + 64 + 32 + 16 + 8 + 4 +
2 + 1 = 1023
2. The BCD adder to add two decimal digits needs minimum of
a) 6 full adders and 2 half adders
b) 5 full adders and 3 half adders
c) 4 full adders and 3 half adders
d) 5 full adders and 2 half adders
Answer: (d)
Solution:
Therefore, BCD adder needs 5 full adders and 2 half adders
1
3. Which one of the following circuits is NOT equivalent to a 2-
input XNOR (exclusive NOR) gate?
a)
b)
c)
d)
Answer: (d)
Solution:
All A, B, C represent EX-NOR & D represent EX-OR
2
4. Consider the following multiplexer where I0, I1, I2, I3, are four
data input lines selected by two address line combinations A1 A0
= 00, 01, 10, 11 respectively and f is the output of the multiplex
(or). EN is the Enable input.
The function f (x, y, z) implemented by the above circuit
a) x y ̅
b) x y + z
c) x + y
d) None of the above
Answer: (a)
Solution:
Output: f (x, y, z)
Z = 0 the only MUX get ends
Characteristic exp:
EN(� � 1� , � � 0� . 0 + � � 1�, 0 . 1 + 1 � � 0� . 2 + 1 0 . 3)
= (( )1)1. 1. + (( )1)1. . + 1. 1. + 1. . 1)
= 1. . + + 1. 1. + . 1. 1
= xy 1
3
5. We consider the addition of two 2's complement numbers bn-1
bn-2 …… b0 and an-1 an-2 . . . . . . a0. A binary adder for adding
unsigned binary numbers is used to add the two numbers. The
sum is denoted by Cn-1 Cn-2 …… C0 and the carry-out by Cout
Which one of the following options correctly identifies the
overflow condition?
a) C out ( � � � �−�1��⨁��� � � �−�1�
b) an-1 bn-1 � � � �−�1�+ � � � �−�1�� � � �−�1�� � � �−�1�
c) C out⨁ −1
d) an-1⨁ −1⨁ −1
Answer: (c)
Solution:
Addition of two positive numbers (or) two negative numbers
then only overflow occurs.
Case 1: two (3bit) positive numbers
+3 = 011 = 2 1 0
+2 = 010 = 2 1 0
← 01 → 2
0101
in the case over flow = . C2
Case 2: two (3bit) negative numbers in 2’s
−3 = 1 0 1 2
−2 = 0 1 0
← 1 0 0 0
1011
in the case over flow = . C2
4
here C2 = Cn-1 [since = 3 bit number] so condition for overflow
= . Cn-1 + −1 = Cout ⨁ Cn-1
6. The RST 7 instruction in 8085 microprocessors is equivalent to:
a) CALL 0010 H
b) CALL 0034 H
c) CALL 0038 H
d) CALL 003C H
Answer: (c)
Solution:
Software interrupt Vector address
RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H
7. Linux operating system uses
a) Affinity Scheduling
b) Fair Preemptive Scheduling
c) Hand Shaking
d) Highest Penalty Ratio Next
Answer: (b)
5
Solution:
Linux OS user two process-scheduling algorithms a “time-
sharing algorithm” for fair preemptive scheduling between
multiple process and a “real-time algorithm” for tasks where
absolute priorities are more important than fairness
8. Find the maximum clock frequency at which the counter in Fig.,
can be operated. Assume that the propagation delay through
each flip-flop and each AND gate is 10 ns. Also assume that the
setup time for the JK inputs of the flip-flops is negligible.
Answer: 25MHz
Solution:
In TCK ≥ + = 10ns + (10 + 10 + 10)ns
min = 40 ns
max = 1 = 1000 *106 = 25MHz
40 40
9. Consider the following midterm expression of F(P, Q, R,
S)=∑ (0, 2, 5, 7, 8, 10, 13, 15)
The minterms 2, 7, 8 and 13 are 'don't care' terms. The minimal
sum-of-products form for F is
a) Q ̅ + � S
b) � � + QS
6
c) � � ̅ + � R ̅ + Q � S + QRS
d) � � ̅ + � QS + PQS + P � ̅
Answer: (b)
Solution:
F (P, Q, R, S) = Σm (0, 5, 10, 15) + Σd (2, 7, 8, 13)
F (P, Q, R, S) = QS + QS
10. Which of the following is termed as minimum error code?
a) Binary code
b) Gray code
c) Excess 3 code
d) Octal code
Answer: (b)
Solution:
The reflected binary code also known as Gray code is a binary
numeral system where two successive values differ in only one
bit. Gray codes are widely used to facilitate error correction in
digital communication.
7
11. A multiplexor with a 4-bit data select input is a
a) 4: 1 multiplexor
b) 2 : 1 multiplexor
c) 16 : 1 multiplexor
d) 8 : 1 multiplexor
Answer: (a)
12. What is the result of the expression (1 & 2) + (3/4)?
a) 1
b) 2
c) 3
d) 0
Answer: (d)
Solution:
(1&2) is a bitwise AND operation,
(3/4) given 0 as integer result.
Therfore, (1&2) + (3/4) = 0+0 = 0
13. Which of the following is an EDI standard?
a) ANSI X.15
b) ANSI X.14
c) ANSI X.13
d) ANSI X.12
Answer: (d)
Solution:
The accredited standards committee X. 12(also Known as ASC
X.12) is standard organization. Character by the American
8
National Standard Institute (ANSI) in 1979. It develops and
maintains content inspired component architecture (CICA)
standards along with XML schema which drive business process
globally
14. Consider the circuit given. Which one of the following options
correctly represents f(x, y, z)?
a) x ̅ + xy + � z
b) x ̅ + xy + � � �
c) xz + xy + � � �
d) xz + x � + � z
Answer: (a)
Solution:
MUX 1 Expression z1 x + z y1 = A
MUX2 Expression
y1 A + YX = (x z1 + y1 z) y1 + xy
⟹ x z1 + y1 z + xy
15. In the given network of AND and OR gates f can be written as
9
a) X0X1X2…Xn + X1X2…Xn + X2X3…Xn + ⋯+ Xn
b) X0X1 + X2X3 +…Xn−1 Xn
c) X0 + X1 + X2 + ⋯ + XnX0 + X1+X2 +⋯ + Xn
d) X0X1 + X3…Xn−1 + X2X3 + X5…Xn−1 + ⋯ + Xn−2 Xn−1 + Xn
Answer: (a)
16. identify the numbers:
List-I List-II
A. USART 1. 8251
B. Micro Controller 2. 8051
C. Interrupt controller 3. 8259
D. DMA controller 4.8257
Codes:
A B CD
a) 1 2 3 4
b) 2 1 4 3
c) 3 4 1 2
d) 4 1 2 3
Answer: (a)
Solution:
A USART (universal synchronous / asynchronous
receiver/transmitter) is manufacture by integrated circuit. Small
device C compiler as 8051
One of best Known Programmable interrupt controller is
8259A, was included in the X86PC
8257 is known as microprocessor 8257 DMA controller
10
17. The addition of 4-bit, two's complement, binary numbers 1101
and 0100 results in
a) 0001 and an overflow
b) 1001 and no overflow
c) 0001 and no overflow
d) 1001 and an overflow
Answer: (a)
Solution:
1101
0100
overflow 1 0 0 0 1
18. The circuit shown in the given figure is a
a) full adder
b) shift register
c) full subtractor
d) decade counter
Answer: (b)
Solution:
The circuit shown in the question is of a full subtractor which is
constructed by the help of two half sub tractors.
11
19. P is a 16-bit signed integer. The 2's complement representation
of P is (F87B)16. The 2's complement representation of 8* P is
a) (C3D8)16
b) (187B)16
c) (F878)16
d) (987B)16
Answer: (a)
Solution:
�11�1�1 1 1�00 0 0�11 �11�0�1 �10�0�0
3 8
20. The functional difference between SR flip-flop and JK flip-
flop is that
a) JK Flip-flop is faster than SR flip-flop
b) JK flip-flop has a feedback path
c) JK flip-flop accepts both inputs 1
d) none of them
Answer: (c)
Solution:
JK flip flop accepts both input as 1 whereas S-R flip flop given
different output when both inputs are 1 i.e., undefined behavior
when both input are 1.
21. a channel of 3 KHZ bandwidth and signal to noise ratio of 30
dB, the maximum data rate is
a) 3000 bps
b) 6000 bps
12
c) 15000bps
d) 30000bps
Answer: (d)
Solution:
According to Shannon’s thermos
C = B log2 (1 + S/N)
Where,
⟹ 10 log10 (S/N) = 30 dB
⟹ log10 (S/N) = 3
⟹ S/N = 103 = 1000
Therefore
C = 3×103 log2 (1 + 1000)
= 3000 log2 (1001)
= 3000 × 9.97 = 29910 = 29.9 kbps
Which is a little less than 30 kbps
22. Advantage of synchronous sequential circuits over
asynchronous ones is
a) faster operation
b) ease of avoiding problems due to hazard
c) lower hardware requirement
d) better noise immunity
Answer: (b)
Solution:
It is easier to avoid hazards in synchronous circuit as compared
to synchronous circuits
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At the same time, it does not have fastest operations as
compared to synchronous circuits
23. The number of full and half-adders required to add 16-bit
numbers is:
a) 8 half-adders, 8 full-adders
b) 1 half-adder, 15 full-adders
c) 16 half-adders, 0 full-adders
d) 4 half-adders, 12 full-adders
Answer: (b)
Solution:
For n-bit number addition = (n – 1) F.A + 1 H.A is required.
24. Let f (A, B) = A' + B Simplified expression for function f (f(x
+ y, y), z) is
a) (x' + z)
b) x y z
c) xy' + z
d) None of the above
Answer: (c)
Solution:
((x + y)’ + y)’ + z = (x’ y’ +y)’ + z
= (x +y) (y’) + z
= xy’ + z
25. Essential hazards may occur in:
a) Combinational logic circuits
b) synchronous sequential logic circuits
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c) Asynchronous sequential logic circuits working in the
fundamental model
d) Asynchronous sequential logic circuits working in the
pulse mode
Answer: (c)
Solution:
Essential hazard due to delay I different latches of different flip-
flop. This results in the logic not
Performing its function property, the three different most
common kinds of hazards are usually referred to as static,
dynamic and functions hazards
These hazards may occur in synchronous sequential logic
circuits working in the fundamental model
26. The hexadecimal representation of 6578 is:
a) 1AF
b) D78
c) D71
d) 32F
Answer: (a)
Solution:
(657)8 1 1 0 1 0 1 1 1 1 = (IAF)16
27. The encoding technique used to transmit the signal in giga
Ethernet technology over fiber optic medium is
a) Differential Manchester encoding
b) Non Return to zero
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c) 4B / 5B encoding
d) BB / 10B encoding
Answer: (d)
Solution:
8B/10 B encoding is the encoding technique used to transmit the
signal in giga Ethernet technology over fiber optic medium. 8
B/10 B maps 8-bit symbols to10 bit symbols to achieve DC
balance.
28. Which of the following operations is commutative but not
associative?
a) AND
b) OR
c) NAND
d) EXOR
Answer: (c)
29. An example of a self-complementing code is:
a) 8421 codes
b) Gray code
c) Excess-3 code
d) 7421 codes
Answer: (c)
Solution:
The 2421, the excess-3 and the 84-2-1 codes are examples of
self-complementing codes, such codes have the property that the
9’s complement of a decimal number is obtained directly by
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changing 1’s to 0’s and 0; s to 1’s (i.e., by complementing each
bit in the pattern)
The necessary condition for a code to be self-complementary is
that the sum of all of its weight must be equal to 9.
i.e., 84 ‒ 2 ‒ 1(8 + 4 ‒ 2 ‒ 1 = 9) and 2421(2 + 4 + 2 + 1 = 9)
30. The virtual address generated by a CPU is 32 bits. The
Translation Look-aside Buffer (TLB) can hold total 64-page
table entries and a 4-way set associative (i.e. with 4-cache lines
in the set). The gage size is 4 KB. The minimum size of TLB tag
is
a) 12 bits
b) 15 bits
c) 16 bits
d) 20 bits
Answer: (c)
Solution:
Given, page size is 4 KB = 212 bytes
So, offset bit is 12
Number of bits used for indexing = 32 – 12 = 20 bits
Number of sets = 64 = 16 = 24
4
Therefore, tag bits are = 20 – 4 = 16 bits
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