Digital Logic Design Test - 4 - PDF Flipbook

Digital Logic Design Test - 4

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GATE
CSE

DigitalLogic
Design

Test-04Solutions


DIGITAL LOGIC DESIGN
1. What is the result of the following expression? (1 &2) + (3&a)

a) 1
b) 3
c) 2
d) 0
Answer: (d)
Solution:
Given (1 & 2) + (3 & 4) in decimal
= (001 & 010) + (011 & 100) in binary
= (000) + (000) = (000)
= 0 in decimal
2. Consider the circuit in fig. which has a four-bit binary number
b3b2b1b0 as input and a five-bit binary number d4d3d2dld0 as
output. The circuit implements:

a) Binary to Hex conversion
b) Binary to BCD conversion
c) Binary to grey code conversion
d) Binary to radix-12 conversion
Answer: (d)

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Solution:

Binary to Radix-12 conversion

3. How many 32K × 1 RAM chips are needed to provide a

memory capacity of 256K-bytes?

a) 8

b) 32

c) 64

d) 128

Answer: (c)

Solution:

Given structure = 32K×1

Required structure = 256K×8

Number of RAM = 256 ×8 = 218×23 = 64
32 ×1 215×20

It required 8 parallel line in each parallel line 8 serial RAM

chips are required

4. The Excess-3 decimal code is a self-complementing code

because

a) The binary sum of a code and its 9's complement is equal to 9

b) it is a weighted code'

c) Complement can be generated by inverting each bit Patter'

d) The binary sum of a code and its10's complement is equal to

9

Answer: (c)

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Solution:
The 2421, the axcess-3 and the 84-2-1 codes are examples of
self-complement of a decimal number is obtained directly by
changing 1’s to 0’s and 0’s to 1’s (i.e., by complementing each
bit in the pattern)
Also, if the sum of the weight is 9 then it is self-complementing
Eg: 5211 = (5 + 2 + 1 + 1) = 9
2421 = (2 + 4 + 2 + 1) = 9
The weighted code is those that obey the position weighting
principle, which states that the position of each number
representing a specific weight
A self-complementary code(excess-3) need not be weighted
code(BCD) and vice-versa
5. Complete each of the following sentences in List-I on the left-
hand side by filling in the word or phrase from the List-II on the
right-hand side that best completes the sentence:
List-I
i. Determining whether you have built the right system is called
ii. Determining whether you have built the system right is

called_____
iii. ______is the process of demonstrating the existence of

defects or providing
iv. _____ is the process of devising the cause of a defect and

fixing it.

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List-II
A. Software testing
B. Software verification
C. Software debugging
D. Software validation
Codes:

I II III IV
a) B D A C
b) B D C A
c) D B C A
d) D B A C
Answer: (c)
Solution:
Software verification: Determine whether you have built the
system right
Software validation: Determining whether you have built the
right system
Software testing is a process of demonstrating the existence of
defects or providing confidence that they do not appear to be
present
Software debugging is process of discovering the cause of
defect and fixing it

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6. Match the following:
List-I

A. Controlled inverter
B. Full adder
C. Half adder
D. Binary adder

List-II
1. a circuit that can add 3 bits
2. a circuit that can add two binary numbers
3. a circuit that transmits a binary word orient its 1's

complement
4. a logic circuit that adds 2 bits
Codes:

A BCD
a) 3 2 4 1
b) 2 4 1 3
c) 3 4 1 2
d) 3 1 4 2
Answer: (d)
Solution:
Circuit that can add 2 bits and 3 bits are half adder and full adder
reprehensively
Binary adder is a circuit that can add two binary numbers
Controlled inverter complements the bits

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7. Consider a preemptive priority-based scheduling algorithm

based on dynamically changing priority. Larger priority number

implies higher priority. When the process is waiting for CPU in

the ready queue (but not yet started execution), its priority

changes at a rate a = 2. When it starts running, it priority

changes at a rate b = 1. All the processes are assigned priority

value 0 when they enter ready queue. Assume that the following

processes want to execute:

Process ID Arrival Time Service Time

P1 0 4

P2 1 1

P3 2 2

P4 3 1

The time quantum Q = 1 When two processes want to join ready

queue simultaneously, the process which has not executed

recently is given priority. The finish time of processes P1, P2,

P3 and p4 will respectively be

a) 4 5, 7 and 8

b) 8, 2, 7 and 5

c) 2,5,7 and 8

d) 8, 2, 5 and 7

Answer: (b)

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8. Consider the 4-to-1 multiplexer with two select lines S1 and S0
given below

The minimal sum-of-products form of the Boolean expression

for the output F of the multiplexer is
a) � Q + Q � + P � R
b) � Q + � Q � + PQ � + P � R
c) � QR + � Q � + Q � + P � R
d) PQ �

Answer: (a)

Solution:

As per the definition of MUX output equation is

F = � 1 � 0 0 + � 1 0 1 + 1 � 0 2 + 1 0 3

0 = 0; 1 = 0; 0 = Q; 1 = P;
2 = 0; 3 = � ;

F = � � + P � R + PQ �

= � + � Q � + P � + P Q �

= Σm(2, 3, 5, 6) = � Q + Q � + P � R

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9. A multiplexer combines four 100-Kbps channels using a time

slot of 2 bits. What is the bit rate?

a) 100 Kbps

b) 200 Kbps

c) 400 Kbps

d) 1000 Kbps

Answer: (c)

Solution:

Since, multiplexer combines four 100 kbps channel, so, bit rate

is

b = 4 × 100 Kbps = 400 Kbps

Time in 2 bit slot so = 400
2

= 200 Kbps

10. Consider a multiplexer with X and Y as data inputs and Z as

control input. If z = 0 selects input x, and z = 1 selects input Y.

what are the connections required to realize the 2- variable

Boolean function f = T + R without using any additional

Hardware?

a) R to X, I to Y, T to Z

b) T to X, R to Y, T to Z

c) T to X, R to Y, O to Z

d) R to X, O to Y, T to Z

Answer: (a)

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Solution:

11. Which of the following statement(s) is (are) not correct?
i. The 2's complement of 0 is 0.
ii. ln 2's complement, the left most bit cannot be used to
express a quantity.

iii. For an n-bit word (2's complement) which includes the sign
bit, there are 2 −1 positive integers, 2 +1 negative integers
and one 0 for a total of 2 unique states.

iv. ln 2's complement the significant information is contained in
the 1's of positive numbers and 0's of the negative numbers.

a) i and iv
b) i and ii
c) iii
d) iv
Answer: (c)
Solution:
The 2’s complement numbers have the following characteristics,
the left most bit cannot be used to express a quantity it is a sign
bit, if it is 1 then number is negative otherwise positive

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12. In the Karnaugh map shown below, X denotes a don't care
term. What is the minimal form of the function represented by
the Karnaugh map?

a) � . ̅ + � . �
b) � . � + � . ̅ + � . . ̅
c) � . ̅ + � . . ̅
d) � . � + � . ̅ + � . ̅

Answer: (a)

Solution:

Quad: � ̅, Quad: � ̅

13. The Excess-3 code is also called

a) Cyclic Redundancy Code

b) Weighted Code

c) Self-Complementing Code

d) Algebraic Code

Answer: (c)

Solution:

Excess-3 code also called self-complementary non-weighted

code because 1's complement of an excess-3 number is the

excess-3 code for 9's complement of the corresponding decimal

number.

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14. If the queue is implemented with a linked list, keeping track of
front pointer and a read pointer, which if these pointers will
change during an insertion into a non-empty queue
a) Neither of the pointers change
b) Only front pointer changes
c) Only rear pointer changes
d) Both of the pointers changes
Answer: (c)
Solution:
Queue is an abstract data type or a linear data structure, in which
the first elements is inserted from
One end called REAR, and the deletion of existing element
takes place from other end called as FRONT

So during the insertion, the rear pointer need to be incremented
and the data is inserted at the memory location currently pointed
by rear pointer
15. The logic circuit given below converts a binary code y1, y2, y3
into

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a) Excess-3 code
b) Gray code
c) BCD code
d) Hamming code
Answer: (b)
Solution:
X1 = Y1
X2 = X1 ⨁ Y2
X3 = X1 ⨁ X2 ⨁ Y3
Represent none of the above given code, for consecutive binary
numbers 011 and 100 gray code should be 010 and 110 but
according to given circuit it comes 010 and 111 respectively i.e.,
toe consecutive binary numbers gray code can different only
single bit but here not the case
16. Identify the operation which is communicative but not
associative?
a) OR
b) NOR
c) EX-OR
d) NAND
Answer: (b)
Solution:
Commutative: x*y = y*x ∀x, y ∈ S
Associative: x*(y*z) = (x*y)*z ∀x, y, z ∈ S

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Therefore,
b. Commutative: x ↓ y = y ↓ x
Associative: (x ↓ y) ↓z ≠ x↓(y ↓ z) ↑
d. Commutative: x ↑ y = (y ↑ x)
Associative: x↑ (y ↑ z) ≠ (x ↑y) ↑z)
17. What cannot replace ‘?’ in the following C-code to print all
odd numbers less than 100?

For (i = 1;?; i = i + 2)
Printf (“%d\n”, i);
a) i ≤ 100
b) i ≤ 101
c) i < 100
d) i < 101
Answer: (b)
Solution:
Since, 101 is an odd number, so, i ≤ 101 will include 101 also,
but we want only number less than 100
18. Which are the essential primes implicating of the following
Boolean function?
f (a, b, c) = a1c + ac1 + b1c
a) a1c and ac1
b) a1c and b1c
c) a1c only
d) ac1 and bc1
Answer: (a)

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Solution:
F (a, b, c) = a’c + ac’+b’c
Minterms Σ (1, 3, 4, 5, 6)
Essential prime implicates

19. Consider the following sequence of instructions:
a = a (+) b, d = (+) b, a = b (+) a This Sequence

a) retains the value of the a and b
b) complements the value of a and b
c) swap a and b(d)
d) negates values of a and b
Answer: (c)
Solution:
Assume a and b are some binary number
A = 10101110
B = 10001010

a) a = a⨁b = 00100100
b) b = a⨁b = 10101110
c) a = a⨁b = 10001010
new value
a = 10001010
b =10101110
so, it swaps value of a and b

14


20. The number of 1's in the binary representation of (3*4096 +
15*256 + 5*16 + 3) are:
a) 8
b) 9
c) 10
d) 12
Answer: (c)
Solution:
3 × 4096 + 15 × 256 + 5 × 16 + 3 = (3F53)16
Hence, total ten 1’s is required in the binary representation

21. (1217)8 is equivalent to
a) (1217)16
b) (028 F)16
c) (2297)10
d) (OB17)16
Answer: (b)
Solution:
(1217)8 = (001010001111)2 = (28 F)16

22. Consider the circuit shown below. ln a certain steady state, Y
is at logical '1’. What are possible values of A, B, C?

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a) A = 0, B = 0, C = 1
b) A = 0, B = C = 1
c) A = 0, B = C = 0
d) A = B = 1. C = 1
Answer: (a)
Solution:
F = � � � � � �.� � . = ( + � ).
When the output is at logic 1 the output equation is 1 = (Af +
� ).C. to justify this equation ‘C’ must be always ‘1’
So, C =1, A = 1, B = 0
Or A = 1, B = 1
Or A = 0, B = 0
23. The channel capacity of a band-limited Gaussian channel is
given by:
a) B log2�2 + �
b) B log2�1 + �
c) B log10 �1 + �
d) B loge�1 + �
Answer: (b)
Solution:
An application of the channel capacity concept to an additive
white Gaussian noise channel B Hz bandwidth and signal-to-
noise

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ratio S/N is the Shannon-Hartley Theorem:
C = B log2�1 + � C is measured in bits per second
24. One of the main features that distinguish microprocessor from

micro-computers is
a) Words are usually larger in microprocessors.
b) Words are shorter in microprocessors.
c) Microprocessor does not contain I/O devices.
d) None of the above
Answer: (c)
Solution:
A microprocessor is a computer processor which incorporates
the functions of a computers control processing unit (CPU) on a
single integrated circuit(IC), or at most a few integrated circuits
A microcomputer is a small, relatively, inexpensive computer
with a microprocessor as its control processing unit (CPU), it
includes a microprocessor, memory and minimal input/output
(I/O) circuitry mounted on a single printed circuit board
That means, microprocessor does not contain input/output
devices
25. 12-bit 2's complement of -73.75 is
a) 01001001.1100
b) 11001001.1100
c) 101 10110.0100
d) 10110110.1100
Answer: (c)

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Solution:
+ 73.75 = 01001001.1100
Taking 2’s complement we get 10110110.0100
26. Software Configuration Management is the discipline for
systematically controlling
a) The changes due to the evolution of work products as the

project proceeds
b) The changes due to defects (bugs) being found and then

fixed.
c) The changes due to requirement changes
d) All of the above
Answer: (d)
Solution:
Software configuration management (SCM) is the task of
tracking and controlling changes in the software, part of the
large cross disciplinary field configuration management, SCM
practices include revision control and the establishment of
baselines
27. The output of the following combinational circuit

a) X. Y
b) X + Y
c) X⨁Y

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d) � � �⨁��� �
Answer: (d)
Solution:

Given circuit is:

Function f = (�� � ̅�.� �� � )�.��(�� �� ��.�� � � �)
f = (�� � ̅�.� �� � )�.��(�� �� ��.�� � � �)
f = ( ̅ . � )+ (x . y)
f = x⨀y = � � ⨁��� �
28. Identify the logic function performed by the by the circuit
shown

a) exclusive OR
b) exclusive NOR
c) NAND
d) NOR
Answer: (b)
Solution:
Given logical circuit is:

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f = ((x + (x + y)’)’ + (y + (x + y)’)’)’
= (x + (x + y)’)” (y + (x + y)’)”
= (x + (x + y)’) (y + (X + y)’)
= (x + x’y’) (y + x’y’)
= ((x + x’) (x’ + y’) (y + y) (y + x’))
= (x + y’) (x’ + y)
= xx’+ xy + x’y’ + y’y’
= xy + x’y’
= (x⨀y)
= x ((EXNOR)y

29. The output Y of the given circuit

a) 1
b) 0
c) X
d) X1
Answer: (b)

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Solution:
On first XOR gate, input 0 is provide which will result in 0,
again for the second and third XOR gate, input 0 will be there,
hence the final output will be 0 since 0 ⨁ 0 = 0
30. Consider the partial implementation of a 2-bit counter using T
flip-flops following the sequence 0-2-3-1-0, as shown below.

To complete the circuit, the input X should be
a) Q21
b) Q2 + Q1
c) (Q1⨁ Q2)1
d) (Q1⨁ Q2)
Answer: (d)
Solution:

Q2 Q1 T2 T1
10 10
10 01
11 10
01 01

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