# Digital Logic Design Test - 3 - PDF Flipbook

Digital Logic Design Test - 3

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GATE
CSE

DigitalLogic
Design

Test-03Solutions

DIGITAL LOGIC DESIGN
1. The simplified SOP (Sum of Product) from the Boolean

expression (P + � + � ).(P + Q + R).(P + Q + � ) is
a) ( � .Q + � )
b) (P + Q. � )
c) (P. � + R)
d) (P.Q + R)
Solution:
(P + � + � ).(P + Q + R).(P + Q + � )

Hence, the expression is (P + Q � )
2. Consider n-bit (including sign bit) 2's complement

representation of integer numbers. The range of integer values
N, that can be represented is____ ≤ N ≤ _____
a) (‒ 2n-1, + 2n-1 ‒ 1)
b) (‒2n, + 2n-1 ‒ 1)
c) (‒2-1, + 2n-1 ‒ 1)
d) (‒2, + 2n-1 ‒ 1)

1

3. if carrier modulated by a digital bit stream, has one of the
possible phase of 0 90, 180 and 270 degrees, then modulation
called
a) BPSK
b) QPSK
c) QAM
d) MSK
Solution:
Quadrature phase sift keying (QPSK) is from of phase shift
keying in which two bits are modulated at once, selective one or
four possible carrier shifts (0, 90, 180, or 270 degrees), QPSK
allows the signal to carry twice as much information as ordinary
PSK using the same bandwidth
Binary phases shift keying(BPSK) is a digital modulation
scheme that conveys data by charging, or modulation, two
different phases of a reference signal the carrier curve) the
constellation points chosen are usually positioned with uniform
angular spacing around a circle

4. The 2's complement representation of the decimal value - 15 is
a) 1111
b) 11111
c) 111111
d) 10001

2

Solution:
+ 15 = 0 1 1 1 1
‒ 15 = 2’s complement of positive number ‒15 = 1 0 0 0 1
5. What is the following sequence of steps taken in designing a
fuzzy logic machine?
a) Fuzzification → Rule evaluation → Defuzzification
b) Fuzzification → Defuzzification → Rule evaluation
c) Rule evaluation → Fuzzification→ Defuzzification
d) Rule evaluation → Defuzzification →Fuzzification
Solution:
Fuzzification → Rule evaluation → Defuzzification
When designing a fuzzy logic, we first have to define the fuzzy
sets and make appropriate member functions, then role
evaluation comes which matches the sets to its corresponding
rules (a series of if then statements)
The other option are simply rearrangements of correct answer
and are obviously wrong
6. Which one of the following is decimal value of a signed binary
number 1101010, if it is in 2, s complement form?
a) ‒ 42
b) ‒ 22
c) ‒ 21
d) ‒ 106

3

Solution:
If MSB (most significant bit) of 2’s complement representation
is 1 then number is negative
(Magnitude is 2’s complement) else number is positive itself
Since MSB of given 2’s complement representation is 1, so,
given number is negative and its magnitude is:
⟹ 2’s complement of 1101010
⟹ 0010101 + 1 = (0010110)2
⟹ (22)10

S, number is ‒ 22
7. The Boolean expression for the output f of the multiplexer

shown below is

a) � � �⊕���� � � �⊕���� �
b) P⊕Q⊕R
c) P + Q + R
d) � � �+��� � � �+��� �
Solution:

f = � � + � � + � � +

4

8. The control signal functions of a 4-bit binary counter are given

below (where X is "don't care"):

1 XXX Clear to 0
0X0 0 No change
0↑01 Count Next

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the
counter starts at 0, then it cycles through the following
sequences:
a) 0, 3, 4
b) 0, 3, 4, 5
c) 0, 1, 2, 3, 4
d) 0, 1, 2, 3, 4, 5
Solution:
When counter reaches 0101 it clears all bits. Load is zero. Hence
input does not affect the counting sequence.

5

9. The period of a signal is 10 MS. What is its frequency in1erlz?

a) 10

b) 100

c) 1000

d) 10000

Solution:

Frequency = 1

= 1
10×10−3

= 1
10−2

= 100Hz

10. Consider the following Boolean expression for F: F(P, Q, R, S)
= PQ + � QR + � Q � S. The minimal sum-of-products form of F

is

a) PQ + QR + QS

b) P + Q + R + S
c) � + � + � + ̅
d) � R + � � S + P

Solution:

F (P, Q, R, S) = PQ + PQR + PQRS = Σm (5, 6, 7, 12, 13, 14,

15)

This on simplification with K-map gives

PQ + QR + QS

6

11. Transform the following logic circuit (without expressing its
switching function) into an equivalent logic circuit that employs
only 6 NAND gates each with 2-inputs.

a)

b)

c)

d)
12. Which of the following 2 input Boolean logic functions is
linearly inseparable?
i. AND
ii. OR
iii. NOR
iv. XOR
v. NOTXOR
a) (i) and (ii)
b) (ii) and (iii)

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c) (iii), (iv) and (v)
d) (iv) and (v)
Solution:
XOR is linearly inseparable, if XOR is, then swapping the labels
on the points will not alter the structure of the space, and NOT
XOR is just XOR with the 1’s swapping with 0’s and vice-versa
13. Given the following Karnaugh map, which one of the
following represents the minimal Sum-Of-Products of the map?

a) xy + y'z
b) wx'y' + xy + xz
c) w'x + y'z + xy
d) xz + y
Solution:

8

14. How much space will be required to store the bit? map of a 1

.3 GB disk with 512 bytes block size?

a) 332.8 KB

b) 83.6 KB

c) 266.2 KB

d) 256.6 KB

Solution:

In bitmap one bit is used for each block

Given, Total memory = 1.3 GB

Block size = 512 bytes

Hence number of blocks = 1.3GB

(This will be size of bitmap in bits) 512 bytes = 1.3×230 bit
29

= 1.3×230 bytes = 332.8 KB
29×8

15. Consider the following Boolean function with four variables F

(w, x, y, z) = L (1, 3, 4, 6, 9, 11, 12, 14). The function is:

a) Independent of one variables

b) Independent of two variables

c) Independent of three variables

d) Dependent on all variables

Solution:

F (w, x, y, z) = xz1 + x1 z

9

16. What is the Boolean expression for the output f of the
combinational logic circuit of NOR gates given below?

a) � � ��+���� �
b) � � �+���� �
c) � � �+���� �
d) � � �+��� � � �+��� �
Solution:

f = � � ��+��� � � � . � � ��+���� � � � � � � �( � + � ). � ( � + � � � �)
= � . �
= � � ��+��� �

10

17. ADMA controller transfers 32-bitwords to memory using cycle

Stealing, the words are assembled from a device that transmits

characters at a rate of 4800 characters per second, The CPU is

fetching and executing instructions at an average rate of one

million instructions per second. By how much the CPU will be

slowed down because of the DMA transfer?

a) 0 06%

b) 0.12%

c) 1.2%

d) 25%

Solution:

As, 1 character = 1 byte

Transfer time = 32
4800

= 4
4800

= 1 sec
1200

given 1 million instruction are fetching and executing in 1

seconds out of which 1200 words are executing though cycle

stealing = 1200 × 100 s = 0.12%
1×106

18. The base (or radix) of the number system such that the

following equation holds is _____ 312 = 13.1
20

11

Solution:
Symbols used in this equation are 0,1,2,3 Hence base or radix
can be 4 or higher
(312)x = (20)x (13.1)x
3x2 + 1x + 2x0 = (2x + 0) (x + 3x0 + x-1)
3x2 + x + 2 = (2x) � + 3 + 1 �
3x2 + x + 2 = 2x2 + 6x + 2
x2 ‒ 5x = 0
x (x ‒ 5) = 0
x = 0 (or) x = 5
but x must be greater than 3, so x = 5
19. if two fuzzy sets A and B are given with member ship
functions

µA(x) = {0.2, 0.4, 0.8, 0.5, 0.1}
µB (x) = {0.1, 0.3, 0.6, 0.3, 0.2}
Then the value of µ ∩
a) {0.9, 0.7, 0.4,0.8 0.9}
b) {0.2, 0.4, 0.8, 0.5, 0.1}
c) {0.1, 0.3, 0.6, 0.3, 0.1}
d) {0.7, 0.3, 0.4, 0.2, 0.7}
Solution:
Given two fuzzy set
A(x) = {0.2, 0.4, 0.8, 0.5, 0.1}

12

B(x) = {0.1, 0.3, 0.6, 0.3, 0.2}
So,
A∪B(x) = {0.2, 0.4, 0.8, 0.5, 0.2}
And
� � �∪�� � (x) = {0.8, 0.6, 0.2, 0.5, 0. 8}
� � �∪�� � (x) = 1 – {0. 1, 0.3, 0.6, 0.3, 0.1}
Similarly,
� � �∪�� � (x) = 1 – {min ( Ai, Bi), ∀ }

= 1 – {0. 1, 0.3, 0.6, 0.3, 0.1}
= –{0. 9, 0.7, 0.4, 0.7, 0. 9}
20. Consider the equation (123)5 = (x8)y with x and y as unknown.
The number of possible solutions is _____.
Solution:
1235 = x8y
1 × 52 + 2 × 51 + 3 × 50 = x.y1 + 8xy0
25 + 10 + 3 = xy + 8
Xy = 30
Possible solutions:
i. X = 1, y = 30
ii. X = 2, y = 15
iii. X = 3, y = 10
Y > 8 and y > x
3 possible solutions

13

21. Consider the circuit in fig shown. It implements

a) ̅ � C + ̅B ̅ + ABC
b) A + B + C
c) A⊕B⊕C
d) AB + BC + CA
22. interrupts which are initiated by an instruction are
a) internal
b) External
c) Hardware
d) software
Solution:
A software interrupt is caused either by an exceptional condition
in the processor itself, or a special instruction in the instruction
set which causes an interrupt when it executed
Hardware interrupts are used by devices to communicate that
they required attention from the operation system

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23. Which of the following functions implements the Karnaugh
map shown below?

a) ̅B + CD
b) D (C + A)
d) (C + D) ( ̅ + D) (A + B)
Solution:
Don't cares are not helping SOP minimization.
24. ln a distributed computing environment, distributed shared
memory is used which is
a) Logical combination of virtual memories on the nodes.
b) Logical combination of physical memories on the nodes
c) Logical combination of the secondary memories on
d) all the nodes.
Solution:
Distributed shared memory is a form of memory architecture
where physically separated memories can be addressed as one

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25. Let r denote number system radix. The only value(s) of r that
satisfy the equation √121r = 11r is/are
a) decimal 10
b) decimal 11
c) decimal 10 and 11
d) any value > 2
Solution:
Verification: For r = 3, 4, 5,……..∞

26. What will be the output of the following logic diagram?

a) X OR y
b) X AND y
c) x XOR y
d) x XNOR y
Solution:
Given logical diagram is

Therefore, function f is:

16

F = (x. � ) + ( ̅.y) = x � + ̅y = x ⨁ y
F = x(EXOR)y
27. Consider the following circuit with initial state Q0 = Q1 = 0.
The D Flip-Flops are positive edge triggered and have set up
times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C; the clock
period of C ≥ 40 nanosecond. Which one is the correct plot of
Y?

a)
b)
c)
d)

17

Solution:
clock D0 = x D1 = X � 0 Q0 Q1 = y

0‒ ‒ 00

10 0 00

21 1 11

31 0 10

41 0 10

51 0 10

60 0 00

Output Y is logic 1 at 2nd clock pulse only, for remaining clock

pulses the output is at logic zero.

28. The 16-bit 2's complement representation of an integer is 1111

1111 1111 0101; its decimal representation is _____.

Solution:

Integer size is 16 bit, already it is given in its 2's complement

notation; So, when it is 2's complemented once again it gives

29. The advantage of MOS devices over bipolar devices is that

a) it allows higher bit densities and also cost effective

b) it is easy to fabricate

c) it is higher-impedance and operational speed

d) all of these

18

30. A circuit outputs a digit in the form of 4 bits. 0 is represented
by 0000, 1 by 0001, ...., 9 by 1001. A combinational circuit is to
be designed which takes these 4 bits as input and outputs 1 if the
digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates
may be used, what is the minimum number of gates required?
a) 2
b) 3
c) 4
d) 5