Digital Logic Design Test - 1 - PDF Flipbook

Digital Logic Design Test - 1

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GATE
CSE

DigitalLogic
Design

Test-01Solutions


DIGITAL LOGIC DESIGN
1. BNA Company needs to develop a digital signal processing

software for one of its newest inventions. The software is
expected to have 20000 lines of code. The company needs to
determine the effort in person-months needed to develop this
software using the basic COCOMO model. The multiplicative
factor for this model is given as 2.2 for the software
development on embedded systems, while the exponentiation
factor is given as 1.5. What is the estimated effort in person-
months?
a) 196.77
b) 206.56
c) 199.56
d) 210.68
Answer: (a)
Solution:

For basic cocomo model
Effort is formulated E = a(KLOC)b
Where a = 2.2 and b = 1.5
KLOC is given as 20000 LOC = 20KLOC
E = 2.2(20)1.5

= 196.77-person month

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2. A software company needs to develop a project that is estimated
as 1000 function points and is planning to use JAVA as the
programming language whose approximate lines of code per
function point is accepted as 50. Considering a = 1.4 as
multiplicative factor, b = 1.0 as exponent ion factor for the basic
COCOMO effort equation and c = 3.0 as multiplicative factor, d
= 0.33 as exponent ion factor for the basic COCOMO duration
equation, approximately how long does the project take to
complete?
a) 11.2 months
b) 12.2 months
c) 13.2months
d) 10.2months
Answer: (b)
Solution:
For basic COCOMO model;
Effort = a(KLOC)b person moths
A = 1.4, b = 1.0
LOC =1000 × 50 = 50000 = 50KLOC
So, Effort = 1.4(50)1.0 = 70 person months
C = (Effort)d months
C = 3, d = 0.33
Development time = 3(70)0.33
= 3 × 4.1 = 12.3(approx.)

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3. How many of the following declarations are correct?
int z = 7.0;
double void = 0.000;
short array [2] = {0, 1, 2};
char c = "\n";
a) None
b) One is correct
c) Two are correct
d) All four are correct
Answer: (b)
Solution:
int z = 7.0; correct and allowed.
Double void = 0.000; wrong because we cannot have a keyword
as a variable name.
Short array [2] and we have assigned 3 elements, 0, 1, 2.
Char c =””; wrong because we cannot assign anything within
double quotes to a character variable

4. What is decimal equivalent of BCD 1 10011 1100?
a) 22.0
b) 22.2
c) 20.2
d) 21.2
Answer: (b)
Solution:
Given BCD code is: 11011.1100

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Convert it into valid pairs=0001 1011.1100
BCD is weight code which is 8421 but BCD
Code has 0-9 digits only. We add 0110 on each invalid group of
4-bits. Therefore,

=0001 1011. 1100
+0000 0110 0110
0010 0010. 0010

In 8421 code = 00100010.0010
Convert it into decimal = 22.2
5. Code optimization is responsibility of:
a) Application programmer
b) System programmer
c) Operating system
d) All of the above
Answer: (b)
Solution:
Code optimization is any method of code optimization to
improve code quality and efficiency. A program may be
optimized so that it becomes a smaller size, consumes less
memory, executes more rapidly or perform fewer input/output
operations.
Application programmers write programs to handle a specific
job, such as a program to track inventory within an organization.

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Systems programmers writes program to maintain and control
computer systems software, such as operating system and
database management systems.
6. If N2 = (7601)8 where N is a positive integer, then the value of n
is
a) (241)4
b) (143)6
c) (165)7
d) (39)16
Answer: (b)
Solution:

N2 = (7601)8
⟹ N2 = 7 × 88 + 6 + 82 + 0 × 81 + 1 × 80

⟹ N2 = 3969
⟹ N = 63

Considering option (b) i.e., (143)6, it can be written as
= 1 × 62 + 4 × 61 + 3 × 60
= 36 + 24 + 3 = 63

7. The characteristic equation of a JK flip flop is:
a) Qn+1 = J. Qn + K. Qn
b) QN+1 = J. � n + � . Qn
c) Qn+1 = Qn J. K
d) Qn+1 = (J+ K) Q
Answer: (b)

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Solution:

Jk flip-flop:

JQ
Clk Q

k

Characteristics table of JK flip-flop:

J K Qn+1

0 0 Qn
0 10
1 01
1 1 Qn

Characteristic equation is
Qn+1 = � � � Qn + J � + JK � n

= J � n+ � Qn

8. The next state table of a 2-bit saturating up-counter is given

below.

Q1 Q1 1+1 0+
0001

0110

1011

1111

The counter is built as a synchronous sequential circuit using T

flip-flops. The expression for T1 and T0 are
a) T1 = Q1Q0, T0 = � 1 � 0
b) T1 = � 1 Q0, T0 = � 1 � 0
c) T1 = Q1 + Q0, T0 = � 1 + � 0

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d) T1 = � 1 Q0, T0 = Q1 + Q0
Answer: (b)

Solution:

Q1 Q1 T1 T0
000 1

011 0

101 1

1 1 →saturated
T1 = � 1Q0
T0 = � 1 + � 0

9. Which function does NOT implement the Karnaugh map given

below?

Wz → 00 01 11 10

xy↓

00 0 × 0 0

01 0 × 1 1

11 1 0 1 1

10 0 × 0 0

a) (w + x)y

b) x y + y w
c) (w + x) ( � + y)( ̅ + y)

d) None of the above

Answer: (d)

Solution:

All the (a, b, c) are realizable

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10. The scheme of which interpreter translates the source program is
known as
a) Paragraph by paragraph
b) instruction by instruction
c) Line by line
d) None of the above
Answer: (c)
Solution:
At interrupter is also program that translates a high-level
language into a low-level one, but does it as the moment the
program is run. You write the program using a text editor or
something similar, and then instruct the interpreter to run the
program it takes the program, one line at a time, and translates
each line before running it; it translates the first line and run it,
then translates the second line and runs it etc.

11. (A + B)�A��B� is equivalent to
a) A⊕ B
b) A ⊙ B
c) (A ⊕ B) ⊙ A
d) (A ⊙ B) ⊕ A
Answer: (a)
Solution:
Given Boolean expression
= (A + B) (� � � � )
= (A + B) ( � + � ) (using Demorgan’s law)

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= (A ̅ + A � + � B + B � )
= (0 + A � + ̅B + 0) (using demerging’s law)
= (A � + ̅B)
= A ⊕ B = ( � � �⊙���� � )

12. Consider the following circuit: to make it a Tautology the?

should be;

x

f

y ?

a) NAND gate
b) AND gate
c) OR gate
d) EX-OR gate
Answer: (a)
Solution:

F = ((x + y) + (x? y))
a. F = ((x + y) + (� � �.� � ))

= ((x + y) + ( ̅ + � ) = 1
b. F = ((x + y) + (x . y)) = X + Y
c. F = ((x + y) + (x + y)) = x + y
d. F = ((x + y) + (x ⊕ y) = ((x + y) + x � + ̅ ) = x + y

9


13. 'FAN IN' of a component A is defined as
a) Count of the number of components that can call, or pass
control, to a component A
b) Number of components related to component A
c) Number of components dependent on component A
d) None of the above
Answer: (a)
Solution:
Fan –in is number of components that can call or pass control to
component A and Fan-out is number of components that are
called by component A.

14. A modulus -12 ring counter requires a minimum of
a) 10 flip-flops
b) 12 flip-flops
c) 8 flip-flops
d) 6 flip-flops
Answer: (b)
Solution:
in a ring counter, to generate 'n' states, n flip flops are required.
Since it is a modulus 12 ring counter. Hence 12 flip-flops are
required.

15. An analog signal has a bit rate of 6000 bps and a baud rate of
2000 baud' How many data elements are carried by each signal
element?
a) 0.336 bits/baud

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b) 3 bits/baud

c) 120,00,000 bits/baud

d) None of the above

Answer: (b)

Solution:

Number data elements are carried by each signal elements are

= = 6000 = 3 bits/baud
2000

16. Consider a single perception with weights as given in the

following figure:

And f(t) defined as f(t) = �01,, > 0 the above perception can
≤ 0

solve

a) OR problem

b) AND problem

c) XOR problem

d) All of these

Answer: (b)

Solution:

Perception after multiplying weight with input will give:

⟹1 (‒1.5) + x.1+ y.1 = f(t)

⟹f (t) = x + y ‒ 1.5

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According to given definition of f(t)
If f (t) = 1, if t > 0 else f(t) = 0 So, truth table is;

x y f(t)
00 0
01 0
10 0
00 1
Eg. if x = 0, y = 0
⟹ f(t) = ‒ 1.5 I but implement xz is
implement.

19. If w, x, y, z are Boolean variables, then which one of the
following is INCORRECT?
a) w x + w (x + y) + x(x + y) = x + w y
b) � � � � �̅(� � � �+��� � �)̅ + � + + �
c) (w ̅ (y + x ̅) + � ̅)y = x �
d) (w + y)(w x y + w y z) = w x y + w y z
Answer: (c)
Solution:
(w ̅(y + xz) + � ̅)y = x �
W ̅y + � ̅y = x �
̅y = x � = false

20. A chip having "150 gates will be classified as
a) SSL
b) MSI
c) LSI
d) VLSI
Answer: (c)

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Solution:

Name Logic gates numbers

SSI(small scale investigation) 1 to 12

MSI(Medium) 13 to 99

LSI(large) 100 to 9999

VLSI(very large) 10,000 to 99,999

ULSI(extra-large) 10,0000 and more

Therefore, 150 logic gates having LSI (large scale integration)

21. The range of representable normalized numbers in the floating-

point binary fractional representation ina32-bitwordwithl-bitsign

8-bit excess l28 biased exponent and 23-bit mantissa is

a) 2-128 to (1 ‒ 2-23) * 2127

b) (1 ‒ 2-23) *2-127 to 2128

c) (12-23) *2-127 to 223

d) 2-129 to (1 ‒ 2-23) *2127

Answer: (d)

Solution:

To evaluate postfix expression, we need operand stack given

expression is infix, so convert it into postfix. So, resulting

postfix expression AB*CD*E/+

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So, total 5push and 9 pop. We can reduce POP since keep one
operation instead of 2 pop. So can be answer but if 5 push and 8
POP given then ‘b’ is wrong.
22. Binary symmetric channel uses
a) Half duplex Protocol
b) Full duplex Protocol
c) Bit oriented Protocol
d) None of the above
Answer: (a)
Solution:
A binary sympatric channel is a common communication
channel model used in coding theory and information theory in
this model transmitted wishes to send a bit (0 or1) and receiver a
bit. At a time only one node can send and on there will be in
receiving mode. It used half-duplex protocol.
23. Which activity is included in the first pass of two pass
assemblers?
a) Build the symbol table
b) Construct the intermediate code
c) Separate mnemonic opcode and operand fields
d) None of these
Answer: (a)
Solution:
All given option (a), (b) and (c) are included in the first pass of
assembler.

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24. Phase transition for each bit are used in
a) Amplitude modulation
b) Carrier modulation
c) Manchester encoding
d) NRZ encoding
Answer: (c)
Solution:
Manchester encoding (also known as phase encoding) is a line
code in which the encoding of each data bit is low then high, or
high then low. A logic '0' is indicated by a '0' to '1' transition at
the center of the bit and the logic '1' is indicated by a '1' to '0'
transmission at the center of the bit.

25. The characteristic equation of the D flip-flop is:
a) Q n+ t = �
b) Q n+ t = D
c) Q n+ t = 1
d) Q n+ t = 0
Answer: (b)
Solution:

D-flip-flop is:
DQ

clk Q

17


Characteristic table is

D Qn+1

00
01

Excitation table is Qn+1 Qn 0
D 1
D Qn Qn
0 0
00 1
01 Qn 0
10

11

Characteristic equation is Qn+1 =D

26. You are given an OR problem and a XOR problem to solve"
Then, which one of the following statements is true?
a) Both OR and XOR problems can be solved using single
layer perception.
b) OR problem can be solved using single layer perception and
XOR problem can be solved using self-organizing maps.
c) OR problem can be solved using radial basis function and
XOR problem can be solved using single layer perception.
d) OR problem can be solved using single layer perception and
XOR problem can be solved using radial basis function.
Answer: (d)
Solution:
OR logical gate: single layer perception.
XOR logic gate: Radial basic function

18


27. What is the minimal form of the Karnaugh map shown below?
Assume that X denotes a don't care term.

a) � ̅
b) � ̅ + � ̅
c) � ̅ + a � d̅
d) � ̅ + � ̅ + ̅ ̅
Answer: (b)
Solution:

28. Consider the circuit shown below. The output of a 2:1 Mux is
given by the function (ac'+ bc).

Which of the following is true?

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a) F = x1’ + x2
b) F = x1’x2 + x1x2’
c) F = x1x2 + x1’x2’
d) F = x1 + x2’
Answer: (c)
Solution:

G = � a + C. b ⟹ � � 1�(1) + x1(0) = � � 1�
Output of MUX 2 ⟹ f = ̅a + C.b
⟹ � � 1�{g} + x2x1
29. The following diagram represents a finite state machine which
takes as input a binary number from the least significant bit.

a) It computes l's complement of the input number
b) It computes 2's complement of the input number
c) It increments the input number
d) It decrements the input number
Answer: (b)
Solution;

input output
00
11
01
01

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I/P = 0 0 1 0
O/P = 1 1 1 0
Output is the 2's complement value for input.
30. The number of digit 1 present in the binary representation of 3
* 512 + 7 × 64 + 5 × 8 + 3 is
a) 8
b) 9
c) 10
d) 12
Answer: (b)
Solution:
= 3 × 512 + 7 × 64 + 5 × 8 + 3
⟹ (2 + 1)29 + (22 + 2 + 1)26 + (22 + 1)23 + (2 + 1)
⟹210 + 29 + 28 + 27 + 26 + 25 + 23 + 21 + 20
⟹11111101011
Therefore, total number of 1’s is 9.

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