Digital Electronics & Microprocessors Test - 3 - PDF Flipbook

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GATE
EEE

DigitalElectronics
&

Microprocessors

Test-03Solutions

DIGITAL ELECTRONICS AND MICROPROCESSORS
1. In 8085A microprocessor, the operation performed by the

instruction LHLD 2100H is
a) (H) ← 21H, (L) ← 00H
b) (H) ← M(2100H), (L) ← M(2101H)
c) (H) ← M(2101H), (L) ← M(2100H)
d) (H) ← 00H, (L) ← 21H
Answer: (c)
Solution:
LHLD 2100 H
L ← M (2100)
H ← M (2101)
2. Intel 8085A and 8086A differ in
a) number of address lines
b) number of data lines
c) operating frequency
d) all of these
Answer: (d)
3. What is the effect of a DAD H instruction?
a) To shift each bit one position to the right with a zero inserted

in MSB position.
b) To shift each bit one position to the left with a zero inserted

in LSB position.
c) To shift each bit one position to the right.
d) To shift each bit one positron to the left.

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Answer: (b)
Solution:
DAD: Add register pair to H and L Register PAD H implies that
content of H and L are added to itself. So content are doubled. It
is as if value in HL pair is multiplied by 2. It shifts each bit
position to left with 0 at LSB
e.g. H-L pair (0505) H
DAD H:

4. An 'Assembler' for a microprocessor is used for

a) assembly of processors in a production line

b) creation of new programmes using different modules

c) translation of a program from assembly language to machine

language

d) translation of a higher level language into English text

Answer: (c)

5. Which one of the following statements is correct? In 8085 μP,

the READY signal is useful when the CPU communicates with

a) a PPI chip

b) a DMA controller chip

c) a slow peripheral chip

d) a fast peripheral chip

Answer: (c)

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Solution:

READY - Active low signal, input to 8085 as an external

request from slow peripheral to indicate that peripheral is not yet

ready for data transfer between processor and peripheral device.

6. An Intel 8085 processor is executing the program given below.

MVI/A, 10H

MVI/B, 10H

BACK: NOP

ADD/B

RLC

JNC BACK

HLT

The number of times that the operation NOP will be executed is

equal to

a) 1

b) 2

c) 3

d) 4

Answer: (c)

7. The content of the accumulator in an 8085 microprocessor is

altered after the execution of the instruction

a) CMP C

b) CPI 3A

c) ANI 5C

d) ORA A

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Answer: (c)
Solution:
Compare instructions (CMPC & CPI 3A.) execution doesn't
alter content of operands involved in comparison. And, ORA A
instruction retains the value in A.
8. Match List-I (Name of Memory) with List-II (Features/
Characteristics) and select the correct answer:
List-I
A. SRAM
B. ROM
C. PLA
D. DRAM
List-II
1. This contains conventional storage like latches (BJT or

MOSFET) and it is non-volatile.
2. This contains conventional storage like latches (BJT or

MOSFET) and has both Read and Write operation.
3. This contains a set of AND, OR or INVERT logic gates and

can be programmed.
4. This contains only MOSFETs and needs periodic refreshing
Codes:

A BC D
a) 3 4 2 1
b) 2 1 3 4
c) 3 1 2 4

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d) 2 4 3 1

Answer: (b)

Solution:

DRAM - MOSFET, periodic refreshing-4

ROM – Read only operation-1

SRAM – Both read and wire operation-2

PLA – AND, OR, INVERT logic gate, programmable-3

9. Which List-I (Interrupts) with List-II (corresponding

characteristics) and select the correct answer using the codes

given below the lists:

List-I List-II

a) TRAP 1. Level triggered

b) INTR 2. Non maskable

c) RST 7.5 3. For increasing the number of interrupts

d) RST 6.5 4. Positive edge triggered

Codes:

A BC D

a) 2 4 3 1

b) 1 4 3 2

c) 1 3 4 2

d) 2 3 4 1

Answer: (d)

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10. DAA is an instruction in the instruction set of many
microprocessors. This instruction is used in a microprocessor to
perform
a) Binary addition
b) BCD addition
c) ASCII addition
d) Binary subtraction
Answer: (b)
Solution:
DAA: Decimal adjust accumulator after addition. The contents
of accumulator are changed into its 2 digit BCD equivalent.
It adjusts the sum of 2-BCD value to create a BCD result. DAA
instruction is carried cut after ADD instruction.

11. After an arithmetic operation, the Flag register of a 8085
microprocessor has the following look:
D7 D6 D5 D4 D3 D2 D1 D0
1 0×1×0×1
The arithmetic operation has resulted in
a) A carry and an odd parity has resulted in
b) Zero and the auxiliary carry Flag being set
c) A number with even parity and 1 as the MSB
d) A number with odd parity and 0 as the MSB
Answer: (a)

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12. Consider the following statements:
1. A total of about one million byes can be directly addressed by
the 8086 microprocessor.
2. The 8086 has thirteen 16-bit registers.
3. The 8086 has eight flags.
4. Compared to 8086 the 80286 provides a higher degree of
memory protection.
Of these statements:
a) 2, 3 and 4 are correct
b) 1, 3 and 4 are correct
c) 1, 2 and 4 are correct
d) 1, 2 and 3 are correct
Answer: (a)

13. Match List-I (Character) with List-II (Interpretation) and
select the correct answer using the code given below the lists:
List-I
A. Colon (:)
B. Blank ( )
C. Comma (,)
D. Semicolon (;)
List-II
1. Separates operation and operand fields
2. Separates operands
3. Beginning of comment field
4. End of label field

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Codes:
ABCD

a) 2 3 4 1
b) 4 1 2 3
c) 2 1 4 3
d) 4 3 2 1
Answer: (b)
Solution:
A. Colon – Used as end of a label field – 4
B. Blank – Separator for operation field and operand 1
C. Comma – Used as a separator for operand – 2
D. Semi-colon – Beginning of comment field – 3
14. The voltage comparator shown in Fig. can be used in the
analog-to-digital conversion as

a) a 1-bit Quantizer
b) a 2-bit Quantizer
c) a 4-bit Quantizer
d) a 8-bit Quantizer
Answer: (a)
Solution:
V0 can assume any one value of two possible ‘0; and ‘1’. Hence
it acts as 1-bit Quantizer.

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15. The reference bit is used for the purpose of
a) Implementing LRU page replacement algorithm
b) Implementing NRU (Not Recently used) algorithm
c) To check if the page table entry is in cache memory
d) Check if the page has been written into recently
Answer: (b)

16. In a memory map the lowest address of an 8K byte is 100H.
What is the highest address?
a) 8192 H
b) 2FFFH
c) 7FFFH
d) 3000 H
Answer: (b)
Solution:
Size of RAM = Highest Address-Lowest address + 1
Highest address =?
Lowest address = (1000) H
Size = 8 K byte = (2000)H
(2000)H = x – (1000)H + (0001)H
x = 2 FFF H

17. A memory system has a total of 8 memory chips, each with 12
address lines and 4 data lines. The total size of the memory
system is
a) 32 k bytes
b) 48 k bytes

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c) 64 k bytes
d) 16 k bytes
Answer: (d)
Solution:
Number of address line: 12
So, number of location: 212
Number of data line: 4
So, such location can store 4 bits
So, size of memory is 212 × 4 bits = 16 K bytes
18. Which one of the following statements is correct? A
microprocessor program written in assembly language is
translated into machine language. The number of instructions in
the machine language when compared with the number of
instructions in assembly language is
a) More only
b) Same
c) Less only
d) Either more or less
Answer: (b)
Solution:
A program written in assembly language is translated into
machine language. Number of instructions in assembly and
machine language is same.

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19. For a memory system, the cycle time is
a) same as the access time.
b) larger than the access time
c) shorter than the access time.
d) sub-multiple of the access time.
Answer: (b)
Solution:

20. Match List-I with List-II and select the correct answer using

the code given below the lists:

List – I List-II

A. ROM 1. Is volatile

B. Static RAM 2. Needs refreshing

C. Dynamic RAM 3. Cannot be written

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Codes:
ABC

a) 1 2 3
b) 3 1 2
c) 2 3 1
d) 3 2 1
Answer: (b)
Solution:
ROM → Read only
SRAM → is volatile
DRAM → Needs refreshing
21. The present micro instruction fetched from a micro
programmed control unit is held in the
a) next address register
b) control address register
c) control data register
d) pipeline register
Answer: (b)
22. In standard TTL gates, the totem pole output stage is primarily
used to
a) Increase the noise margin of the gate
b) Decrease the output switching delay
c) Facilitate a wired OR logic connection
d) Increase the output impedance of the circuit
Answer: (b)

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23. Assertion (A): A key specification of any memory device is its
access time.
Reason (R): The access time of the memory must be more than
the access time of the microprocessor
a) Both A and R are true and R is the correct explanation of A
b) Both A and R are true but R is NOT the correct explanation
of A
c) A is true but R is false
d) A is false but R is true
Answer: (b)

24. Consider the following statements:
1. The process of entering data is called burning in ROM.
2. ROMs are volatile memories.
3. ROMs are used in microcontroller security systems.
What of these statements are correct?
a) 1, 2 and 3
b) 1 and 2
c) 2 and 3
d) 1 and 3
Answer: (d)
Solution:
ROMs are non-volatile as these can be reproduced on
restoration of power.

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25. In memory-mapped I/O scheme, all data transfer instructions of

8085 microprocessors can be used only for

a) Memory devices

b) I/O devices

c) Ports

d) Memory and I/O devices

Answer: (d)

Solution:

In memory mapped I/O scheme, input-output devices are

assigned and identified by 16-bit address. To transfer data

between MPU and I/O devices, memory related instruction like

LDA, STA are used. So, memory instructions can be used for

both memory and I/O devices.

26. Suppose 64 KB, ROM ICs are available in abundance. 1 MB

ROM can be obtained from

a) 16 ICs in a row

b) 16 ICs in a column

c) 8 ICs in a column and 2 ICs in a row

d) None of the above

Answer: (b)

Solution:

1 IC’s size is = 64 KB

so No. of IC’s required for 1 MB = 1 MB
64 KB

= 220B = 24 = 16 IC’s
26 × 210B

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In a column (because are used in parallel not in series)

27. A memory system of 64 K bytes needs to be designed with

RAM chips of 1 K byte each, and a decoder tree constructed

with 2:4 decoder chips with "Enable" input. What is the total

number of decoder chips?

a) 21

b) 64

c) 32

d) 25

Answer: (a)

Solution:

Total memory = 64 K byte

RAM chips are of = 1 K byte

So number of RAM chips required = 64 K byte = 64
1 K byte

In order to address 64 RAM chips number of decorder requires.

Actually we need 64 addresses to address 64 RAM chips.

Now for this we require 6 : [64] decorder requires to design 6 :

64decorder from 2 : 4 decorder is

= 64 + �644� + �1646� = 16 + 4 + 1 = 21
4 4 4

28. Which one of the following statements is correct? The I/O

method used in a micro-controller is

a) Hand shaking

b) Interrupting

c) Direct Memory Access

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d) All three of the above
Answer: (d)
29. Memory-mapped I/O-scheme for the allocation of address to
memories and I/O devices, is used for
a) small systems
b) large systems
c) both large and small systems
d) very large systems
Answer: (a)
Solution:
In case of memory mapped I/O a part of memory is assigned for
I/O devices and rest is for memory so it is done when we have
less number of I/O devices i.e. small system.
30. Assertion (A): Stack is a group of memory locations in RAM
used for temporary storage of data.
Reason (R): PUSH and POP instructions are used to send and
retrieve data from stack.
a) Both A and R are true and R is the correct explanation of A
b) Both A and R are true but R is not the correct explanation of

A
c) A is true but R is false
d) A is false but R is true
Answer: (b)

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Solution:
Both are correct but R is not the reason as there is no assertion-
reason link between the two.

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