Digital Electronics & Microprocessors Test - 2 - PDF Flipbook

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GATE
EEE

DigitalElectronics
&

Microprocessors

Test-02Solutions

DIGITAL ELECTRONICS AND MICROPROCESSORS
1. The TRAP is one of the interrupts available in INTEL 8085.

Which one of the following statements is true of TRAP?
a) It is a level triggered.
b) It is negative edge triggered.
c) It is positive edge triggered.
d) It is both positive edge triggered and level triggered.
Answer: (d)
2. When a program is being executed in an 8085 microprocessor,
its Program Counter contains
a) the number of instructions in the current program that have

already been executed
b) the total number of instructions in the program being

executed
c) the memory address of the instruction that is being currently

executed
d) the memory address of the instruction that is to be executed

next
Answer: (d)
Solution:
Program Counter is a 16 bit ROM Pointer Register that holds
address of next instruction to be fetched.

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3. A DADH instruction is same as
a) Shifting each bit one position to the left
b) Shifting each bit one position to the right
c) Shifting each bit one position to the left with a zero inserted
in LSB position
d) Shifting each bit one position to the right with a zero inserted
in LSB position
Answer: (c)

4. Consider the following statements:
The 16-bit register /register-pair which cannot be stored in stack
using PUSH instruction is
1. HL
2. SP
3. PSW
4. PC
Select the correct answer using the code given below:
a) 1 and 2
b) 1 and 3
c) 2 and 3
d) 2 and 4
Answer: (d)
Solution:
PUSH Rp
Rp → BC, DE, HL, PSW
PSW → Program status word

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5. In 8085 microprocessors, the value of the most significant bit of
the result following the execution of any arithmetic or Boolean
instruction is stored in the
a) carry status flag
b) auxiliary carry status flag
c) sign status flag
d) zero status flag
Answer: (c)

6. Assertion (A): Microcontrollers have the same architecture as a
microprocessor.
Reason (R): Microcontrollers find wide application in
embedded system design.
a) Both A and R are true, and R is the correct explanation of A.
b) Both A and R are true, but R is not a correct explanation of
A.
c) A is true, but R is false.
d) A is false, but R is true.
Answer: (a)
Solution:
Microcontroller like micro-processor has Von Neumann or
Harvard architecture. The instruction set can also be CISC or
RISC. However, microcontroller can be stand-alone system used
in embedded system.

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7. A Direct Memory Access (DMA) transfer implies
a) Direct transfer of data between memory and accumulator
b) Direct transfer of data between memory and HO devices
without the use of microprocessor
c) Transfer of data exclusively within microprocessor registers
d) A last transfer of data between microprocessor and HO
devices.
Answer: (b)

8. In a microprocessor, the address of the next instruction to be
executed, is stored in
a) stack pointer
b) address latch
c) program counter
d) general purpose register
Answer: (c)
Solution:
Program counter in a microprocessor holds address of next
instruction to be executed.

9. The program counter in a 8085 microprocessor is a l6-bit
register because
a) it counts 16 bits at a time
b) here are 16 address at a time
c) it facilitates the user storing 16-bit data temporarily
d) it has to fetch two 8-bit data at a time
Answer: (b)

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10. MVI B, 00H
MVI A, 1CH
DCR B
DAA
STA TEMP
HLT
What is the content of TEMP location after the execution of the
above program?
a) 1C H
b) 22 H
c) 82 H
d) 12 H
Answer: (b)
Solution:
MVI A, (1C) H
Content of accumulator A → 0001 1100
DAA → Decimal adjust accumulator
If value of lower order bits in accumulator > 9 then instruction
adds 06 i.e., 0110 to lower order bits

11. The propagation delay of a digital IC is the difference between
a) initiating clock pulse and triggering of gates
b) the application of input and its presence at the output

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c) the triggering of a Flip-flops and change in its state
d) None of these
Answer: (d)
12. Match List-I with List-II and select the correct answer using
the code given below the lists:
List-I
A. SID, SOD
B. READY
C. TRAP
D. ALE
List-II
1. Wait state
2. Interrupt
3. Serial data transfer
4. Memory of I/O read/write
5. Address latch control
Codes:

ABC D
a) 3 1 5 2
b) 3 1 2 5
c) 4 3 2 5
d) 4 3 1 2
Answer: (b)

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Solution:
• SID, SOD - Serial input data and serial output data.
• READY - Active low signal, input to 8085 as an external

request from slow peripheral to indicate that peripheral is not
yet ready for data transfer. So it indicates a wait state.
• TRAP - Non-maskable interrupt
• ALE - Address latch enable
13. The ECL can be used to switch frequencies as high as
a) 1 MHz
b) 100 MHz
c) 500 MHz
d) 10 MHz
Answer: (c)
14. A single instruction to clear the lower four bits of the
accumulator in 8085 assembly language is
a) XRI OFH
b) ANI FOH
c) XRI FOH
d) ANI OFH
Answer: (b)
15. An instruction cycle is the time in which, a hard-wired
controller completes four functions. What is the correct
sequence of these functions?
a) Fetch - update - decode - execute
b) Fetch - decode - update - execute

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c) Decode - execute - fetch - update
d) Execute - decode - fetch – update
Answer: (a)
Solution:
Step-I: Fetch the code from memory
Step-II: Update the programme counter
Step-III: Decode the instruction code
Step-IV: Execute the instruction
16. In one of the code for transfer of numbers, the code for the
succeeding number differ from that of the number only in the
change of a single digit. The code under consideration is
a) ASCII
b) Excess 3 Code
c) Gray Code
d) None of these
Answer: (c)
17. Among the following four, the slowest ADC (analog-to-digital
converter) is
a) parallel-comparator (i.e., flash) type
b) successive approximation type
c) integrating type
d) counting type
Answer: (c)

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18. As compared to 16-bit microprocessor, 8-bit microprocessor
are limited in
a) speed
b) directly addressable memory
c) data handling capability
d) all of these
Answer: (d)

19. The ASCII Code is for information interchange by a binary
code for
a) numbers only
b) alphabets only
c) alpha numeric and other common symbols
d) none of these
Answer: (c)

20. A 100 K byte memory is managed using variable partitions but
no compaction. It currently has two partitions of sizes 200 K
byes and 260 K bytes respectively. The smallest allocation
request in K bytes that could be denied is for
a) 151
b) 181
c) 231
d) 541
Answer: (b)

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21. The Program Counter in a computer is a special purpose
register which contains
a) the instruction being executed
b) the address of the instruction being executed
c) the next instruction to be expected
d) the address of the next instruction to be executed
Answer: (d)

22. The chip select access time for reading ROM contents is
a) the delay between application of proper chip select signal and
the stable output address
b) the delay between the previous valid output data and the next
change in address
c) the time for which the output data remains valid when the
device is no longer selected
d) maximum time for which the valid address can be changed
Answer: (a)

23. An interrupt in which the external device supplies its address as
well as the interrupt request is called
a) vectored interrupt
b) maskable interrupt
c) non-maskable interrupt
d) designated interrupt
Answer: (a)

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24. The increasing order of speed of data access for the following
devices is
i) Cache Memory
ii) CDROM
iii) Dynamic RAM
iv) Processor Registers
v) Magnetic Tape
a) (v), (ii), (iii), (iv), (i)
b) (v), (ii), (iii), (i), (iv)
c) (ii), (i), (iii), (iv), (v)
d) (v), (ii), (i), (iii), (iv)
Answer: (b)
Solution:
Tape, CD ROM, Dynamic ROM: Cache memory, processor
registers.

25. Which of the following cycle is required to fetch and execute
information?
a) Clock cycle
b) Tricycle
c) Introduction cycle
d) Memory cycle
Answer: (c)

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26. Which of the following I/O methods does not use the CPU for

performing I/O operation?

a) Program initiated I/O

b) Device initiated I/O

c) Direct memory access

d) Serial I/O

Answer: (c)

Solution:

In DMA, high speed data transfer takes place between system

memory and outside peripheral devices like disc. In DMA, MPU

releases the control of the bus to a device called DMA

controller. The controller manages the data transfer between the

memory and a peripheral under its control bypassing

microprocessor.

27. Match List-I (Type of instruction) with List-II (Instruction)

and select the correct answer using the codes given below the

Lists:

List-I List-II

A. One byte instruction 1. MOVA, data.

B. Two byte instruction 2. MOVA, B

C. Three-byte instruction 3. MOVA, M

D. Register indirect addressing 4. JMP addr

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Codes:
ABC D

a) 1 2 4 3
b) 2 1 4 3
c) 2 1 3 4
d) 1 2 3 4
Answer: (d)
28. Stack pointer is a register which comes into use
a) whenever a data is read from the memory
b) whenever a data is written into the memory
c) whenever the output variable is sent out of the CPU
d) whenever an interrupt or high priority call comes from

external devices
Answer: (d)
29. Assembler directives are required
a) only in hand assembling
b) only in machine assembling
c) in hand assembling as well as machine assembling
d) only when there is an operating system
Answer: (b)
Solution:
Translation from assembly language i.e. mnemonics into binary
is done either manually (hand) or by a programme called an
assembler. Assembler directives are the commands given to
assembler directing it to perform operations other than

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assembling instruction. These instructions are not translated not
machine codes.
e.g. END end of assembly
30. In a 8-bit microcomputer having 8K bytes of RAM memory the
length of SP will be
a) 5
b) 8
c) 11
d) 13
Answer: (d)

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