Digital Electronics & Microprocessors Test - 1 - PDF Flipbook

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GATE
EEE

DigitalElectronics
&

Microprocessors

Test-01Solutions

DIGITAL ELECTRONICS AND MICROPROCESSORS
1. If (327)9 = (x)5, then the value of x given by

a) 327
b) 268
c) 2033
d) 3302
Answer: (c)
2. When a "CALL addr” instruction is executed, the CPU carries
out the following sequential operations internally.
Note: (R) means content of register R
((R)) means content of memory locating pointed by R
PC means Program Counter
SP means Stack Pointer
a) (SP) incremented

(PC) ← (Addr)
((SP)) ← (PC)
b) (PC) ← (Addr)
((SP)) ← (PC)
(SP) incremented
c) (PC) ← (Addr)
(SP) incremented
(SP)) ← (PC)
d) (SP)) ← (PC)
(SP) incremented
(PC) ← (Addr)

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Answer: (d)
Solution:
For execution of CALL instruction
Step 1: Current contents of PC is pushed on to stack and SP is
updated.
Step 2: The 16 bit target address given in instruction is moved
into PC.
3. Given the binary 00000111, its 2's complement is obtained and
expressed in hexadecimal form. The result is
a) F8
b) F9
c) -79
d) none of these
Answer: (b)
4. The output of a logic gate is "1" when all its inputs are at logic
"0". The gate is either
a) a NAND or an EX-OR gate
b) a NOR or an EX-OR gate
c) an AND or an EX-NOR gate
d) a NOR or an EX-NOR gate
Answer: (d)

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5. Cached and interleaved memories are ways of speeding up
memory access between CPUs and slower RAM. Which
memory models are best suited (improves performance the
most) for which programs?
1. Cache memory is best suited for small loops.
2. Interleaved memory is best suited for small loops.
3. Interleaved memory is best suited for large sequential
code.
4. Cached memory is best suited for large sequential code.
a) 1 and 2 are true
b) 1 and 3 are true
c) 4 and 2 are true
d) 4 and 3 are true
Answer: (b)

6. Indicate which of the following logic gate can be used to realize
all possible combinational logic functions?
a) AND gates only
b) NAND gates only
c) EX-OR gates only
d) NOR gates only
Answer: (d)

7. What is the addressing mode used in the instruction PUSH B?
a) Direct
b) Register
c) Register indirect

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d) Immediate
Answer: (c)
Solution:
Store the contents of register pair BC on two top locations of the
stack. Address are defined by SP register. So it uses register
indirect addressing mode.
8. A high on RESET OUT line signifies that
a) all the registers of the CPU are being reset
b) all the registers and counters are being reset
c) all the registers and counters are being reset and in addition

this signal can be used to reset external support chips
d) processing can begin when this signal goes high
Answer: (c)
9. The minimal product-of-sums function described by the K-map
given in Fig.

a) A C
b) A + C
c) A + C
d) AC
Answer: (a)

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Solution:

F = A.C
10. A microprocessor is a minimum combination of

a) μP and clock
b) μP, clock and ROMs
c) μP, clock, RAMs and ROMs
d) μP, clock, RAM, ROM, PIA and ACIA
Answer: (d)
11. Consider the following terms which are used to indicate the
time taken while executing instructions:
l. Machine cycle
2. Instruction cycle
3. Time state
What is the correct sequence of these in the ascending order of
the time taken by each?
a) 3 – 2 – 1
b) 1 – 2 – 3
c) 3 – 1 – 2
d) 1 – 3 – 2
Answer: (c)
Solution:

tinstruction > tmachine > tT

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12. In a parallel processing system with processors, each processor
makes a request at most every 2 microseconds and each request
can ask for a maximum of 64 bits. These requests are made over
a high speed shared but with a maximum throughput of 100
megabits. Assume that with each request, 40 bits are required
for transmission of the data-address and protocol.
Approximately, what is the maximum value of t for which the
system can operate without any delays at peak load?
a) 1
b) 2
c) 3
d) 4
Answer: (d)

13. Which of the following is an invalid state in an 8-4-2-l Binary
Code Decimal counter?
a) 1 0 0 0
b) 1 0 0 1
c) 0 0 1 1
d) 1 1 0 0
Answer: (d)
Solution:
1100 is not a valid BCD combination

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14. A microprocessor with 12 address lines is capable of
addressing
a) 1024 locations
b) 2028 locations
c) 4096 locations
d) 64 K locations
Answer: (c)

15. Direct-Memory Access Channel (DMA) facilitates data to
move into and out of the system
a) on first-come first-serve basis
b) with equal time delay
c) without sub - routine
d) without programme intervention
Answer: (d)

16. Which of the following instructions require more number of T-
states?
a) MOV A, B
b) MOV A, M
c) LDAX B
d) DAD D
Answer: (d)
Solution:
DAD D → 1-byte, 10 T-states
MOV A, B → 1-byte, 4 T-states
MOV A, M → 2-bytes, 7 T-states
LDAX B → 1-byte, 7 T-states

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17. SHIFT LEFT instruction causes all bits shifted from one
position to the left with rightmost bit set to zero. The effect is to
a) multiply by 2
b) divide by 2
c) SET the most significant bit
d) none of these
Answer: (a)

18. Intel 80286 microprocessor was designed to serve as the CPU
in a multitasking operating systems as it has
a) 8 MHz operating frequency
b) real address mode to support lower microprocessors of the
same family
c) protection and virtual memory capability
d) signals to interface with co-processor
Answer: (c)

19. Assertion (A): Intel 8085 microprocessor has five hardware
interrupts and eight software interrupts.
Reason (R): All the thirteen of them are vector interrupts.
a) Both A and R are true, and R is the correct explanation of A.
b) Both A and R are true, but R is not a correct explanation of
A.
c) A is true, but R is false.
d) A is false, but R is true.
Answer: (c)

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Solution:
Five hardware interrupts → TRAP, RST 7.5, RST 6.5, RST 5.5,
INTR.
Software → RST 0 to RST 7
INTR is non-vectored interrupt. All 11 other are vectored
interrupt
20. Consider the given circuit. In this circuit, the race around

a) does not occur
b) occurs when CLK = 0
c) occurs when CLK = 1 and A = B =1
d) occurs when CLK = 1 and A = B = 0
Answer: (a)
Solution:
It does not occur, because it is a S - R FF. Race around
condition occurs only in J-KFF when J = K = 1.
21. Which of the following statements is not applicable to serial
transmission of data?
a) One bit at a time
b) Faster method of transmission
c) LSB transferred first
d) Only one wire used
Answer: (b)

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22. During a DMA transfer, the processor (check the incorrect
statement)
a) continues its normal operations
b) suspends its normal operations
c) needs to initiate read (write) command
d) needs to check if the input/output device is ready for data
transfer
Answer: (a)

23. In the figure, as long as X1 = 1 and X2 = 1, the output Q
remains

a) at 1
b) at 0
c) at its initial value
d) unstable
Answer: (d)
Solution:

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24. In a virtual memory system, the address space specified by the
address lines of the CCPU must be ....... than the physical
memory size and ......... than the secondary storage size.
a) smaller, smaller
b) smaller, larger
c) larger, smaller
d) larger, larger
Answer: (b)

25. Match List-I (Function) with List-II (Chip) and select the
correct answer using the code given below the lists:
List-I
A. Continues to block lower priority interrupts until it receives
an EOI command
B. Enables synchronous and asynchronous serial communication
C. Has I/O ports which can be configured as input ports output
ports or can be used to produce control signals
D. Can be programmed to handle all I/O tasks as well as carry
out some data processing
List-II
1. 8255
2. 8089
3. 8259
4. 8251

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Codes:
ABCD

a) 4 3 1 2
b) 3 1 2 4
c) 4 1 2 3
d) 3 4 1 2
Answer: (d)
Solution:
8251 – USART – Universal synchronous asynchronous
receiver/transmitter – B
8255 - Data transfer with simple I/O or interrupt driven I/O
8259 – Programmable interrupt Controller
8089 – I/O processor
26. The register which holds address of the location to or from
which data are to be transferred is called
a) index register
b) instruction register
c) memory address register
d) memory data register
Answer: (c)

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27. The open collector outputs of two 2- inputs NAND gates are
connected to a common pull up resistor. If the input to the gates
are P, Q and R, S respectively, the output is equal to
a) PQ. RS
b) PQ + RS
c) PQ + RS
d) PQRS
Answer: (a)
Solution:

28. A microprocessor is called an n-bit microprocessor depending
on
a) register's length
b) size of internal data bus
c) size of external data bus
d) none of these
Answer: (b)

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29. The maximum integer which can be stored on an 8-bit
accumulator is
a) 2
b) 200
c) 224
d) 255
Answer: (d)

30. Consider the following statements:
The speed imbalance between memory access and CPU
operation can be reduced by:
1. Cache memory
2. Memory interleaving
3. Reducing the size of memory
Which of the above statements is/are correct?
a) 1 only
b) 1 and 2
c) 2 and 3
d) 3 only
Answer: (b)
Solution:
Memory interleaving.
Cache memory: Small size, volatile memory for high speed.
Most often used instruction and data are in cache. It is a static
RAM.

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