Computer Organization Test - 5 - PDF Flipbook
Computer Organization Test - 5
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GATE
CSE
Computer
Organization
Test-05Solutions
COMPUTER ORGANIZATION
1. If the associativity of a processor cache is doubled while
keeping the capacity and block size unchanged, which one of
the following is guaranteed to be NOT affected?
a) Width of tag comparator
b) Width of set index decoder
c) Width of way selection multiplexor
d) Width of processor to main memory data bus
Answer: (d)
Solution:
If associativity is doubled, then number of tag bits will be
increased and set offset size is reduced and size of MUX is
directly proportional to associativity only Physical address size
and Data bus size are not altered.
2. Which one of the following is not an addressing mode?
a) Register indirect
b) Auto increment
c) Relative indexed
d) immediate operand
Answer: (c)
Solution:
Relative indexed is not addressing mode=
1
3. Which of the following switching techniques is most suitable for
interactive traffic?
a) Circuit switching
b) Message switching
c) Packet switching
d) All of the above
Answer: (b)
Solution:
Packet switching is a digital networking communications
method that group all transmitted data into suitably size blocks,
called packets which are transmitted via a medium that may be
shared by multiple simultaneous communication sessions packet
switching increases network efficiency robustness and enables
technological coverage since of many applications operating on
the same network packets are compressed of a header and
payload Packet switching is most suitable for interactive traffic
4. A computer system has a 4K word cache organized in block-set-
associative manner with four blocks per set, 64 words per block.
The number of bits in the SET and WORD fields of the main
memory address format is
a) 15, 40
b) 6, 4
c) 7, 2
d) 4, 6
Answer: (d)
2
Solution:
Block size = 64 words so WORD field size = 6
Bits and associativity is 4
Number of blocks = 4K/64 = 64
Number of sets = 64/4 = 16
So, SET field size is 4 bits
5. If the initial value of register A is Ao, the value of register B
after the program execution will be
a) the number of 0 bits in A0
b) the number of 1 bits in A0
c) A0
d) 8
Answer: (b)
Solution:
The Value in register A is rotated through right 8 times. During
each rotation operation, if carry flag is set the value of register B
is incremented. After 8 rotations B register contains the number
of 1's in register A0.
6. The principle of Locality of reference justifies the use of:
a) Virtual memory
b) Interrupts
c) Cache memory
d) Secondary memory
Answer: (c)
3
Solution:
Locality of reference, also known as the principle of locality, is
a term for the phenomenon in which the same values, or related
strong locations. Are frequently accessed which are present in
cache
The cache memory is smaller, faster memory which stores
copies of the data from frequently used main memory locations
7. Which of the following must be true for the RFE (Return from
Exception) instruction on a general purpose processor?
1. It must be a trap instruction
2. It must be a privileged instruction
3. An exception cannot be allowed to occur during execution of
an RFE instruction.
a) 1 only
b) 2 only
c) 1 and 2 only
d) 1, 2 and 3 only
Answer: (d)
Solution:
A REF (Return from Exception) instruction contains a trap
instruction, privileged instruction and an exception can't be
allowed to occur during the execution of an REF instruction.
8. Banker’s algorithm is for.
a) Deadlock Prevention
b) Deadlock Avoidance
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c) Deadlock Detection
d) Deadlock creation
Answer: (c)
Solution:
The bankers algorithm , sometimes referred to as the avoidance
algorithm, sometimes referred to as the avoidance algorithm
which is used to check after assigning requests resources system
is in safe state deadlock free or not
9. Consider a three word machine instruction
ADDA [R0],@ B
The first operand (destination) "A [R0]" uses indexed addressing
mode with R0 as the index register. The second operand (source)
"@ B" used indirect addressing mode. A and B are memory
addresses residing at the second and the third words,
respectively. The first word of the instruction specific the
opcode, the index registers designation and the source and
destination addressing modes. During execution of ADD
instruction, the two operands are added and stored in the
destination (first operand).
The number of memory cycles needed during the execution
cycle of the instruction is
a) 3
b) 4
c) 5
d) 6
5
Answer: (b)
Solution:
In instruction execution cycle, to get the first operand through
second operand through indirect addressing mode (B), it takes
two index addressing mode it takes one machine cycle. To get
the more machine cycle because B is the address
After the addition is completed the result is to send to the
destination by using the index addressing mode, which requires
one more machine cycle.
So a total of four machine cycles are required to execute the
above instruction.
10. What is true about UML stereotypes?
a) Stereotype is used for extending the UML language
b) Stereotyped class must be abstract
c) The stereotype indicates that the UML element cannot be
changed
d) UML profiles can be stereotyped for backward compatibility
Answer: (a)
Solution:
A stereotype is a one of the tree tapes of extensibility
mechanisms in the unified modeling language, the other two
being tags and constraints.
6
11. Which of the following is not a Unix Command?
a) Whoami
b) WC
c) is
d) Put
Answer: (d)
Solution:
UNIX commands:
1. Ls: Lists files is current directory
2. Wc (file name): Tells you how many lines, word and
characters there are in a file
3. Whoomi: return your user name
12. Horizontal micro programming
a) Does not require use of signal decoders.
b) Results in larger sized microinstructions than vertical
microprogramming
c) Uses one bit for each control signal
d) All of the above
Answer: (d)
13. The test suite (set of test input) used to perform unit testing on a
module could cover 70% of the code. What is the reliability of
the module if the probability of success is 0.95 during testing?
a) 0.665 to 0.95
b) At the most 0.665
c) At the most 0.95
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d) At least 0.665
Answer: (b)
Solution:
Unit testing of the module is covering = 70 % of the code
Probability of success = 0.95
Reliability ≤ 0.7 * 0.95 = 0.665
14. Consider the following sequence of micro-operations
MBR ← PC
MAR ← X
Memory ← MBR
Which one of the following is a possible operation performed by
this sequence?
a) Instruction fetch
b) Operand fetch
c) Conditional branch
d) Initiation of interrupt service
Answer: (d)
Solution:
To execute interrupt cycle, the present content of PC will be
pushed to stack with the help of MBR and MAR before placing
ISR address in PC. (Always only MAR and MBR are used to
address Memory in basic computer).
8
15. Monitor is an intercrosses Communication (IPC) technique
which can be described as
a) it is higher level synchronization primitive and is a collection
of procedures, variables, and data structures grouped together
in a special package.
b) it is a non-negative integer which apart from initialization can
be acted upon by wait and signal operations
c) it uses two primitives, send and receive which are system
calls rather than language constructs.
d) it consists of the IPC primitives implemented as system calls
to block the process when they are not allowed to enter
critical region to save CPU time.
Answer: (a)
Solution:
A monitor is defined as a collection of procedures, variables and
data structures that are all groups together in a special kind of
module or package
Option (b) defines semaphores
Option (c) defines message passing of Interprocess
communication.
16. Which of the following addressing modes permits relocation
without any change what so ever in the code?
a) Indire0t addressing
b) Indexed addressing
c) Base register addressing
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d) PC relative addressing
Answer: (c)
17. A UNIX file system has 1-KB blocks and 4-byte disk addresses.
What is the maximum file size if i-nodes contain 10 direct
entries and one single, double and triple indirect entry each?
a) 32 GB
b) 64 GB
c) 16 GB
d) 1GB
Answer: (c)
Solution:
Maximum possible file size is
= � �3 ×
= �10424�3 × 1024 bytes = 16 GB
18. Assume that 16-bit CPU is trying to access a double word
stating at an odd address. How many memory operations are
required to access the data?
a) 1
b) 2
c) 3
d) 4
Answer: (c)
10
19. Consider a 4-way set associative cache consisting of 128 lines
with a line size of 64 words. The CPU generates a20-bit address
of a word in main memory. The number of bits in the TAG,
LINE and WORD fields are respectively
a) 9, 6, 5
b) 7, 7, 6
c) 7, 5, 8
d) 9, 5, 6
Answer: (d)
Solution:
Address is divided into tag, set, word field
The word fields consists of 6 bits as 26 = 64
The set field consists of 5 bits
Number of sets = 128 = 32 =25
4
So the number of bits in the tag field = 20 – (number of bits for
set field + number of bits for word field) = 20 – 11 = 9 bits
20. In the indirect addressing scheme, the second part of an
instruction contains:
a) the operand in decimal form
b) the address of the location where the value of the operand is
stored
c) the address of the location where the address of the operand
is stored
d) the operand in an encoded form
Answer: (c)
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Solution:
In the indirect addressing mode, the effective address of the
operand is the contest of a register or main memory location
location whose address is given in the instruction; indirection is
noted by placing the name of the register or the memory address
given in the instruction in parenthesis
21. Consider a pipelined processor with the following four stages:
IF : Instruction Fetch
ID : Instruction Decode and Operand Fetch
EX : Execute
WB : Write Back
The IF, ID and WB stages take one clock cycle each to complete
the operation. The number of clock cycles for the EX stage
depends on the instruction. The ADD and SUB instructions need
1 clock cycle and the MUL instruction needs 3 clock cycles in
the EX stage. Operand forwarding is used in the pipelined
processor.
What is the number of clock cycles taken to complete the
following sequence of instructions?
ADD R2, R1, R0 R2 ← R1 + R0
MUL R4, R3, R2, R2 ← R1 * R2
SUN R6, R5, R4, R6 ← R5 ‒ R4
a) 7
b) 8
c) 10
12
d) 12
Answer: (b)
Solution:
Pipeline processor has four stages
IF, ID, EX, WB Clock cycles instruction
1 ADD
1 SUB
3 MUL
Consider the following diagram
CLK S1 S2 S3 S4
1 I0 ‒ ‒ ‒
2 I1 I0 ‒ ‒
3 I2 I1 I0 ‒
4 I2 I1 I0
5 I2 I1 I0
6 I2 I1 I0
7 I2 I1
8 I2
22. interrupt which arises from illegal or erroneous use of an
instruction or data is
a) software interrupt
b) internal interrupt array
c) External interrupt
d) all of the above
Answer: (b)
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Solution:
Internal interrupts a rise from illegal or erroneous use of an
instructions that raises internal interrupts are register overflow,
attempt to divided by zero, an invalid operation code stack
overflow and protection violation
External interrupts generally occur as a result of outside
interface A software interrupt often used to implement system
call
23. Given that r = 7.5, j = -1.0, n = -1.0, n = 1.0, m = 2.0 the value
of –x + j == x > n ≥ m is:
a) 0
b) 1
c) 2
d) 3
Answer: (a)
Solution:
-- x + j = = x > n > = m
Here we need to check LHS = = RHS. So we get answer as 0 or
1 only by applying values
--7. 5 + (-1.0) = = (7.5 > 1.0) = 2.0
(6. 5 – 1.0) = = (0 > 2.0)
(5.5 = = 0)
Return false (0) since 5.5 is not equal to 0
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24. in a digital transmission, the receiver clock is 0.1 percent faster
than the sender clock. How many extra bits per second does the
receiver receive if the data rate is 1 Mbps?
a) 10 bps
b) 100 bps
c) 1000 bps
d) 10000 bps
Answer: (c)
Solution:
At 1 Mbps, the receiver receives 1,001,00 bps instead of 1,00,00
bits sent = 1,001,000 bits received
= 1000 extra bps
Because the receiver is 0.1 percent faster
25. An access sequence of cache block addresses is of length N and
contains n unique block addresses. The number of unique block
addresses between two consecutive accesses to the same block
address is bounded above by k. What is the miss ratio if the
access sequence is passed through a cache of associativity A ≥ k
exercising least-recently used replacement policy?
a) n/N
b) 1/N
c) 1/A
d) k/n
Answer: (a)
15
26. A computer system has a 4K word cache organized in block-set-
associative manner with four blocks per set, 64 words per block.
The number of bits in the SET and WORD fields of the main
memory address format is
a) 15, 40
b) 6, 4
c) 7, 2
d) 4, 6
Answer: (d)
Solution:
Block size = 64 words so WORD field size = 6
Bits and associativity is 4,
Number of blocks = 4k/64 = 64
Number of sets = 64/4 = 16
So, SET field size is 4 bits
27. The main memory of a computer has 2c m blocks while the
cache has 2c blocks. If the cache uses the set associative
mapping scheme with 2 blocks per set, then block k of the main
memory maps to the set:
a) (k mod m) of the cache
b) (k mod c) of the cache
c) (k mod 2c) of the cache
d) (k mod2c. m) of the cache
Answer: (b)
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Solution:
Kth Block of M is placed at
(K MOD S) set, S = 2 = C
2
28. Mechanism that binds code and data together and keeps them
secured from outside world is known as
a) Abstraction
b) inheritance
c) Encapsulation
d) polymorphism
Answer: (c)
Solution:
Encapsulation is an Oop concept that binds to gather the data and
functions that manipulate the data and that keeps both safe from
outside interface and misuse Data encapsulation led to the
important OOP concept of data hiding
Abstraction is a process of hiding the implementation details
from the user
Inheritance enables new objects to take on the properties of
existing objects
Polymorphism in OOP occurs when a parent class reference is
used to refer to a child class object
29. In a function-oriented design, we
a) minimize cohesion and maximize coupling
b) maximize cohesion and minimize coupling
c) maximize cohesion and maximize coupling
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d) minimize cohesion and minimize coupling
Answer: (b)
Solution:
Cohesion refers to the degree to which the elements of a
module/class being together it has to do with the elements
within the module/class Coupling refers to the degree to which
the different modules/Class depend on each other it has to do
with the elements among different modules/classes All good
software has low coupling and high cohesion
30. An N- bit carry look ahead adder, where N is a multiple of 4,
employs ICs 74181 (4bit ALU) and 74182 (4 bit carry look
ahead generator).
The minimum addition time using the best architecture for this
adder is
a) Proportional to N
b) Proportional to log N
c) A constant
d) None of the above
Answer: (a)
Solution:
One IC can provide only for 4 bits addition, so the addition time
is directly proportional to number of chips.
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