Computer Organization Test - 2 - PDF Flipbook

Computer Organization Test - 2

280 Views
30 Downloads
PDF 5,673,686 Bytes

Download as PDF

REPORT DMCA


GATE
CSE

Computer
Organization

Test-02Solutions


COMPUTER ORGANIZATION

1. The speed up of a pipeline processing over an equivalent non-

pipeline processing is defined by the ratio:

a) S = (K + ntn 1)tp
n−

b) S = (K + ntn 1)tp
n+

c) S = (K − ntn 1)tp
n+

d) S = (K + n− 1)tp
ntn

Where,

• N → number of tasks

• → time of completion of each task

• K → number of segments of pipeline

• → clock cycle time

• S → speed up ratio

Answer: (a)

Solution:

A non-pipeline unit that performs the same operation and

makes a time equal to tn to complete each task The total time

requited for n task is n.tn

The case where a k-segment pipeline with a clock cycle time

is tp is used to execute n tasks this first task T1 requires a time

equal to ktp to complete its operation since there are K

segment in the pipe the remaining (n – 1) task emerge from

1


the pipe at the rate of one task per clock cycle and they will be

complicate after a time equal to (n – 1).tp.

Therefore, to complete n tasks using k-segment pipeline

requires k + (n – 1) clock cycles.

The speed –up of a pipeline processing over an equivalent

non-pipeline processing is defined by the ratio

S = (k + n.tn
n − 1).tp

2. The travelling salesman problem can be solved in:

a) Polynomial time using dynamic programming algorithm

b) Polynomial time using branch-and-bound algorithm

c) Exponential time using dynamic programming algorithm or

branch-and-bound algorithm

d) Polynomial time using backtracking algorithm

Answer: (c)

Solution:

One of the earliest application programming is the held-karp

algorithm to solve to solve TCP in time O (n2 2n). It also can

be solved by using branch and bound technique. The travelling

salesman problem is NP-complete problem solved

3. Consider evaluating the following expression tree on a

machine with load-store architecture in which memory can be

accessed only through load and store instructions. The

variables a, b, c, d and e are initially stored in memory. The

binary operators used in this expression tree can be evaluated

by the machine only when the operands are in registers. The

2


instructions produce result only in a register. If no intermediate
results can be stored in memory, what is the minimum number
of registers needed to evaluate this expression?

a) 2
b) 9
c) 5
d) 3
Answer: (d)
Solution:
Instructions produce results in registers only
R ← a, R2 ← b, R1 ← R1 – R2
So R2 is free
R2 ← c, R3 ← d. R2 ← R2 + R3
R3 ← e. R3 ← R3 – R2
R1 ← R1 + R3
So, minimum 3 registers are needed.
Common Data
The following code segment is executed on a processor
which allows only register operands in its instructions; Each
instruction can have at most two source operands and one

3


destination operand, assume that all variables are dead after
this code segment.

c = a + b;
d = c × a;
e = c + a;
x = c × c;
if (x > a)
{
Y = a × a;
}
else
{
D = d × d;
E = e × e;
}
4. The performance of a pipelined processor suffers if
a) The pipeline stages have different delays
b) Consecutive instructions are dependent on each other
c) The pipeline stages share dependent hardware resources
d) All of the above
Answer: (d)
Solution:
Pipeline performance is reduced due to structural dependency,
Data Dependency, Control dependency and when different
stages need different delays.

4


5. Consider that the memory is byte addressable with word size
32 bits, and the program has been loaded starling from
memory location 1000 (decimal). If an interrupt occurs while
the CPU has been halted after executing the HALT instruction,
the return address (in decimal) saved in the stack will be
a) 1007
b) 1020
c) 1024
d) 1028
Answer: (d)
Solution:
PC holds the address 1028

I1 I2 I3 I4 I5
1000 – 1007 1008 – 1011 1012 – 1015 1016 – 1023 1024 – 1027

6. Match the following:
List-I
a) indexed Addressing
b) Direct Addressing
c) Register Addressing
d) Base-indexed Addressing g
List-II
1. is not used when an operand is moved from memory into a
register or from a register to memory.

5


2. Memory address is computed by adding up two registers
plus
an (optional) offset'

3. Addressing memory by giving a register plus content
offset.

4. can only be used to access global variables whose address
is known at compile time

Codes:
AB CD

a) 2 1 4 3
b) 2 4 1 3
c) 3 4 1 2
d) 3 1 4 2
Answer: (c)
Solution:
Indexed addressing is an addressing mode in which effective
addressing is computed by given a register content plus
content offset.
Direct addressing can only be used to access global variable
whose address is known at compile time.
Register addressing is an addressing mode in which the
effective addressing is given by the content of the register
used in the instruction.
Based index addressing, memory address is computed by
adding up to two registers plus an (optimal) offset.

6


7. A processor can support a maximum memory of 4GB, where
the memory is word_ addressable (a word consists of two
bytes). The size of the address bus of the processor is at least
_____ bits.
Answer: 31
Solution:
Word size = 16 bit
So memory size = 231 words.
∴31 address bits are needed.

8. A machine has a 32-bit architecture, with 1-word long
instructions. It has 64 registers, each of which is 32 bits long. It
needs to support 45 instructions, which have an immediate
operand in addition to two register operands. Assuming that
the immediate operand is an unsigned integer, the maximum
value of the immediate operand is _____.
Answer: 16383
Solution:
Word size = 32 bit
Numbers of CPU register 6 bits are needed.
Instruction Opcode size is 32 bits.
Number of supporting instructions = 45, so minimum 6 bits are
needed.
Instruction is having with operation part, Reg1, Reg2 and
immediate operand

7


9. ______is a process model that removes defects before they can
precipitate serious hazards.

a) incremental model
b) Spiral model
c) Cleanroom software engineering
d) Agile model
Answer: (c)
Solution:
Clean Room Software Engineering (CSE) is a process model
that removes defects before they can precipitate serious hazards,
it is a team oriented, theory based software, which is developed
using the formal methods, which is developed using the formal
methods, correctness verification and statistical Quality
Assurance (SQA), clean room management is based on the
incremental model of software development, which accumulated
into the final product.
10. A 5 stage pipelined CPU has the following sequence of stages

IF- Instruction fetch from instruction memory, RD-Instruction
decode and register read, EX – Execute: ALU operation for
data and address computation, MA-Data memory access for
write access the register read at RD stage it used, WB-Register
write back. Consider the following sequence of instructions:

I1: L R0, Loc1; R0 < = M [loc1]
I2: A R0, R0; R0 < = R0 + R0
I3: S R2, R0; R2 < = R2 – R0

8


Let each stage take one clock cycle. What is the number of
clock cycles taken to complete the above sequence of
instructions starting from the fetch of I1?
a) 8
b) 10
c) 12
d) 15
Answer: (b)
Solution:

1 2 3 4 5 6 7 8 9 10
IF RD EX MA WB
nst. IF RD EX MA WB

IF RD EX MA WB

No. of clock cycles 10

11. For all delayed conditional branch instructions, irrespective of
whether the condition evaluate true or false
a) The instruction following the conditional branch instruction
in memory is executed
b) the first instruction in the fall through path is executed
c) the first instruction in the taken path is executed
d) the branch takes longer to execute than any other instruction
Answer: (d)
Solution:
'b' will become correct answer if condition is false only and 'c'
will become correct answer if condition is true only. As

9


condition is not mentioned ’d’ will become correct answer
because 7-10 clock cycles are needed for executing conditional
branch instruction in 8085 microprocessor
12. The capacity of the memory unit is defined by the number of
words multiplied by the number of bits/word. How may
separate address and data lines are needed for a memory of 4K
× 16?
a) 10 address lines, 16 data lines
b) 11 address lines, 8 data lines
c) 12 address lines, 16 data lines
d) 12 address lines, 12 data lines
Answer: (c)
Solution:

12 address lines and 16 data lines
13. Which of the following statements about relative addressing

mode is False?
a) It enables reduced instruction size
b) It allows indexing of array element with same instruction
c) It enables easy relocation of data
d) It enables faster address calculation than absolute

addressing
Answer: (b)
Solution:
Relative addressing cannot be faster than absolute addressing
as absolute address must be calculated from relative address.

10


Is true as instead of absolute address we can use a much
smaller relative address in instructions which results in smaller
instruction size
By using the base address of array we can index array elements
using relative addressing.
Is true as we only need to change the base address in case of
relocation-instructions remaining the same.
14. Arrange the following configurations for CPU in decreasing
order of operating speeds: Hardwired control, vertical
microprogramming, horizontal microprogramming
a) Hardwired control, vertical microprogramming, horizontal

microprogramming
b) Hardwired control, horizontal microprogramming, vertical

microprogramming
c) Horizontal micro-programming, vertical micro-

programming, hardwired control
d) Vertical micro-programming, horizontal micro-

programming, hardwired control
Answer: (b)
Solution:
Fastest Control unit is hardwired control unit and vertical
micro programming control unit is slowest.
15. Compared to CISC processors, RISC processors contain
a) More register and smaller instruction set
b) Larger instruction set and less registers

11


c) less registers and smaller instruction set
d) more transistor elements
Answer: (c)
Solution:
RISC processor has more register and smaller instruction in
comparison to CISC processor.
16. The most appropriate matching for the following pairs
List – I
X. Indirect addressing
Y. Immediate addressing
Z. Auto decrement addressing
List – II
1. Loops
2. Pointers
3. Constants

Codes:
a) X – 3, Y – 2, Z – 1
b) X – l, Y – 3, Z – 2
c) X – 2, Y – 3, Z – l
d) X – 3, Y – l, Z – 2
Answer: (c)
Solution:
Immediate Addressing mode is used for constant access and
indirect mode is for pointers, like auto decrement addressing
used for Loops.

12


17. Which of the following computing models is not an example
of distributed computing environment?
a) Cloud computing
b) Parallel computing
c) Cluster computing
d) Peer-to-peer computing
Answer: (b)
Solution:
Parallel computing is a type of computation in which many
calculations or the execution of process are carried out
simultaneously. Large problem can often be divided into
smaller ones, which can then be solved at same time. Its type
of distributed computing environment
Could computing is a type of internet based computing thet
provided shared computer processing resources and data to
computer and other device on demand. Cluster computing
used in cloud computing.

18. While estimating the cost of software, Lines of Code (LOC)
and Function Points (FP) are used to measure which one of the
followings?
a) Length of code
b) Size of software
c) Functionality of software
d) None of the above
Answer: (b)

13


Solution:
Lines of code(LOC) is a software metric used to mesure the
size of computer of line in the text of the program’s source
code.
A functional point is a”unit of mesurement” to express the
amount of business functionality an information system (as
product) provides to a user. Function points are used to
compute a functional size mesurement of software. The cost
(in dollars or hours) of a signal unit is caliculated from past
projects.
19. A certain moving arm disk-storage, with one head, has the
following specifications: Number of tracks / recording surface:
200 Disk rotation speed :2400 rpm Track storage capacity:
62,500 bits The Average latency of this device is P msec and
the data transfer rate is Q bits/sec. Write the values of P & Q.?
Solution:
T = 200, RPM = 2400, RPS = 40
Track capability = 62,500 bits
One revolution time is 25 ms
Average latency time = 12.5 ms
P = 12.5ms
Q = Data transfer rate = no. of bits/sec
In one second it can complete 40 tracks
Q = 40 × 62500 bits/sec

= 2500000 bits/sec

14


20. Moving Process from main memory to disk is called:
a) Caching
b) Termination
c) Swapping
d) Interruption
Answer: (c)
Solution:
Swapping is a useful technique that enables a computer to
execute programs and manipulate data files large than main
memory.

21. Linking
a) cannot be performed before relocation
b) cannot be performed after relocation
c) can be performed both before and after relocation
d) is not required if relocation is performed
Answer: (a)
Solution:
A physical data structure refers to the actual organization of
data on a storage device.
The logical data structure refers to how the information papers
to a program or users. For example, a data file is a collection of
information stored together
Array is the one data structure which refers to actual memory
organization; stack, table and linked list are logical data
structures.

15


22.A CPU generally handles an interrupt by executing an
interrupt service routine
a) as soon as an interrupt is raised
b) by checking the interrupt register at the end of fetch cycle
c) by checking the interrupt register after finishing the
execution of the current instruction
d) By checking the interrupt register at fixed time intervals.
Answer: (c)
Solution:
A CPU generally handles an interrupt by checking the
interrupt register after finishing the execution of the current
instruction.

23.Match the following with respect to the jump statements:
List-I
a. return
b. go to
c. break
d. continues
List-II
1. The conditional test and increment portions
2. A value associated with it
3. Requires a label for operation
4. An exit from only the innermost loop

16


Codes:
ABC D

a) 2 3 4 1
b) 3 4 1 2
c) 4 3 2 1
d) 4 3 1 2
Answer: (a)
Solution:
The return statement terminates the execution of function
and returns control to the calling function. Are turn statement
can also return a value to the calling function
Go to statement in C programming provides an
unconditional jump from the ‘go to’ to a labeled statement in
the same function.
When a break statement is encountered inside a loop, the
loop is immediately terminated and program control resumes
at the next statement following loop. It can be used to
terminate a case in switch statement.
The continue statement passes control to the next iteration of
the nearest enclosing do for, or while statement in which it
appears, by passing any remaining statements in the do, for,
or while statement body

17


24.Consider a -stage pipeline processor. The number of cycles
needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3,
S4 is shown below.
S1 S2 S3 S4
I1 2 1 1 1
I2 1 3 2 2
I3 2 1 1 3
I4 1 2 2 2
What is the number of cycles needed to execute the following
loop?
For (I = 1 to 2) {11; for (I = 1 to 2) {I1; I2; I3; I4;}
a) 16
b) 23
c) 28
d) 30
Answer: (b)
Solution:
For 1st loop 15 clock cycles and for 2nd loop 8 clock cycles are
sufficient so total number of clocks needed is 23.

25.Assume that for a certain processor, a read request takes 50
nanoseconds on a cache miss and 5 nanoseconds on a cache
hit. Suppose while running a program, it was observed that
80% of the processor's read requests result in a cache hit. The
average read access time in nanoseconds is _____.
Answer: 14

18


Solution:
HC + (1 – H) M = (0.8 × 5) + (0.2 × 50) = 14ns
26. A Trojan horse is
a) A program that performs a legitimate function that is

known to an operating system or its user and also has a
hidden component that can be used for nefarious purposes
like attacks on message security or impersonation.
b) A piece of code that can attach itself to other programs in
the system and spread to other systems when programs are
copied or transferred.
c) A program that spreads to other computer systems by
exploiting security holes like weaknesses in facilities for
creation of remote processes
d) All of the above
Answer: (a)
Solution:
Option (a) defines Trojan horse
Option (a) defines Virus
Option (a) defines Worm
27. n absolute addressing mode
a) the operand is inside the instruction
b) the address of the operand is inside the instruction
c) The register containing the address of the operand is
specified inside the instruction
d) The location of the operand is implicit

19


Answer: (b)
Solution:
Absolute Addressing Mode is also known as memory directs
Addressing Mode.
28.Component level design is concerned with
a) Flow oriented analysis
b) Class based analysis
c) Both of the above
d) None of the above
Answer: (c)
Solution:
Component level design is basically used to defined data
structures algorithms, interface characteristic and
communication mechanism for each software component
identified in the architectures design
It is concerned with both flow oriented analysis and class
based analysis.
29.Which of the following flags are set when 'JMP' instruction is
executed?
a) SF and CF
b) AF and CF
c) All flags
d) No flag is set
Answer: (d)

20


Solution:
The JMP is instruction transfers extension to the address
generated by adding the 8-bit value in the accumulator to the
16-bit value in the DPTR register.
Neither the accumulator nor the DPTR register are altered. No
flags are affected by this instruction.
30.Which of the following statements is true?
a) ROM is a Read/Write memory
b) PC points to the last instruction that was executed
c) Stack works on the principle of LIFO
d) All instructions affect the flags
Answer: (a)

21


Data Loading...