Computer Organization Test - 1 - PDF Flipbook
Computer Organization Test - 1
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GATE
CSE
Computer
Organization
Test-01Solutions
COMPUTER ORGANIZATION
1. Mechanism that binds code and data together and keeps them
secured from outside world is known as
a) Abstraction
b) inheritance
c) Encapsulation
d) polymorphism
Answer: (c)
Solution:
Encapsulation is an OPP concept that binds together the data
and functions that manipulate the data and functions that
manipulate the data and that keep both safe from outside
interface and misuse. Data encapsulation led to the important
OOP concept of data hiding.
Abstraction is a process of hiding the implementation details
from the user.
Inheritance enhances enables new objects to take on the
properties of existing objects.
Polymorphism in OOP occurs when a parent class reference is
used to refer to child class object.
2. Which is not a typical program control instruction
a) BR
b) JMP
c) SHL
d) TST
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Answer: (c)
Solution:
Typical program control instructions:
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST
SHL (shift left) operation is not a typical program control
instruction.
3. Booth's algorithm for integer multiplication gives worst
performance when the multiplier pattern is
a) 101010.....1010
b) 100000.....0001
c) 111111.....1111
d) 011111..... 1110
Answer: (a)
Solution:
In Booth multiplier, more number of consecutive bit changes
needs more number of arithmetical operations
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4. Which of the following is a design criterion for instruction
formats?
a) The size of instructions
b) The number of bits in the address fields
c) The sufficient space in the instruction format to express all
the operations desired'
d) All of these
Answer: (d)
Solution:
Design criteria for instruction formats:
• Size of the instructions.
• Consider the instruction fetch and instruction building
required.
• Include enough bits to definite all operations.
• Determine any address range or size limitations.
5. A CPU has 24-bit instructions. A program starts at address 300
(in decimal). Which one of the following is a legal program
counter (all values in decimal)?
a) 400
b) 500
c) 600
d) 700
Answer: (c)
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Solution:
PC maintains the address of next instruction. Hence PC value
must be incremented by 3 each time.
6. The decimal value 0.5 in IEEE single precision floating point
representation has
a) Fraction bits of 00000...000000 and exponent value '0'
b) Fraction bits of 00000...000000 and exponent value -1
c) Fraction bits of 10000...000000 and exponent value 0
d) No exact representation
Answer: (b)
Solution:
0.5 = 0.102 = 0.10 × 20 = 1.02 × 2-1
Implementation Normalization form = 1.00 × 2-1
So fraction is having with all zeros and exponent is –1.
7. Which one of the following set of UNIX operations always
display “WELCOME”?
a) export title=WELCOME; Echo $title
b) title = WELCOME; export $ title; sh -c "echo $tittle
c) title = WELCOME; export title; sh -c "echo $tittle"
d) title = WELCOME; echo $title
Answer: (c)
Solution:
Given, 12 direct, one indirect and one double 256 bytes and 2
bytes for disk block addresses. Then, maximum possible size
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of File in system is = [12 + (27) + (27)2] × 256 Byte So, none
option is true.
8. Let the clock cycles required for various operations be as
follows:
Register to/from memory transfer: 3 clock cycles
ADD with both operands in register: 1 clock cycle
Instruction fetch and decode: 2 clock cycles per word
The total number of clock cycles required to execute the
program is
a) 29
b) 24
c) 23
d) 20
Answer: (b)
Solution:
I1 (7) I2 (5) I3 (3) I4 (7) I5 (2) = 24 clock cycles
(4 + 3) + (2 + 3) + (2 + 1) + (4 + 3) + (2 + 0)
FE D FD E FD E FD E FD E
9. A processor has 40 distinct instructions and 24 general purpose
registers. A 32-bit instruction word has an opcode, two register
operands and an immediate operand. The number of bits
available for the immediate operand field is_____.
Answer: 16
5
Solution:
32
operation A1 A2 operend
log240 log224 log224 xxx
6 5 5
32-16=16
10. Computers can have instruction formats with
a) only two addresses and three address instructions
b) only one address and two address instructions
c) only one address two addresses and three
d) zero address, one address, two addresses and three address
instruction
Answer: (d)
Solution:
Stack operations uses Zero-address that is there is no address
field in the computational instructions.
One address instructions use an accumulator (AC) register for
all data manipulation.
Two-address instructions are the most common in commercial
computers.
Computers with three-address instruction formats can use
each address field to specify either a process register of
memory operand.
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11. A processor needs software interrupt to
a) Test the interrupt system of the processor
b) Implement co-routines
c) Obtain system services which need execution of privileged
instructions
d) Return from subroutine
Answer: (c)
12. A processor is fetching instructions at the rate of 1 MIPS. A
DMA module is used to transfer characters to RAM from a
device transmitting at 9600 bps. How much time will the
processor be slowed down due to DMA activity?
a) 9.6 ms
b) 4.8 ms
c) 2.4 ms
d) 1.2 ms
Answer: (d)
Solution:
Consider data width of the system bus to be in byte, DMA
will run every cycle for every byte
1 sec → 106 bits
1 sec → 10-6 bits
9600 bit → 9600 ×10-6 sec
9600 B → 9600 × 8 ×10-6 sec = 1.2 ms
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13. The contents of the flag register after execution of the
following program by 8085 microprocessors will be
Program
SUB A
MVI B, (01)H
DCR B
HLT
a) (54)H
b) (00)H
c) (01)H
d) (45)H
Answer: (a)
Solution:
SUB A: z x AC x CY
sp x
010101 Flag
0 1 registers
A=01 H x z x AC x CY
DCR B
sp
0 1 0 1 0 1 0 1 =(5 4)H
14. Which of the following statements about peephole
optimization is False?
a) It is applied to a small part of the code
b) It can be used to optimize intermediate code
c) To get the best out of this, it has to be applied repeatedly
d) It can be applied to a portion of the code that is not
contiguous
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Answer: (d)
Solution:
Peephole optimization is applied over a very small set of
instructions in a segment of generated code. It is used to
optimize the intermediate codes.
15. How many 32K × 1 RAM chips are needed to provide a
memory capacity of 256 K-bytes?
a) 8
b) 32
c) 64
d) 128
Answer: (c)
Solution:
Number of RAM chips required = (256 K × 8)/(32K × 1)
= 64
16. On a non-pipelined sequential processor, a program segment,
which is a part of the interrupt service routine, is given to
transfer 500 6ytes from an I/O device to memory. Initialize the
address register initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address
Register
Increment the address register
Decrement the count
If count! = 0 go to LOOP
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Assume that each statement in this program is equivalent to a
machine instruction which takes one clock cycle to execute if
it is a non-load/ store instruction. The load-store instructions
take two clock cycles to execute. The designer of the system
also has art alternate approach of using the DMA controller to
implement the same transfer. The DMA controller requires 20
clock cycles for initialization and other overheads. Each DMA
transfer cycle takes two clock cycles to transfer one byte of
data from the device to the memory.
What is the approximate speedup when the DMA controller
based design is used in place of the interrupt driven program
based input-output?
a) 3.4
b) 4.4
c) 5.1
d) 6.7
Answer: (a)
Solution:
Non-pipelined system required
(2 + 2 + 1 + 1 + 1) 2 + 7 × 500 cycles = 3502 cycle
DMA clock need = 20 + 2 × 500 = 1020 cycles
Speed up = 3502/1020
= 3.43
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17. For the daisy chain scheme of connecting I/O devices, which
of the following statements is true?
a) It gives non-uniform priority to various devices.
b) It gives uniform priority to all devices.
c) It is only useful for connecting slow devices to a processor
d) It requires a separate interrupt pin on the processor for each
device.
Answer: (a)
Solution:
In daisy chain scheme first device has first priority and last
device has least priority.
18. The main memory of a computer has 2c m blocks while the
cache has 2c blocks. If the cache uses the set associative
mapping scheme with 2 blocks per set, then block k of the
main memory maps to the set:
a) (k mod m) of the cache
b) (k mod c) of the cache
c) (k mod 2c) of the cache
d) (k mod2c. m) of the cache
Answer: (b)
Solution:
Kth Block of MM is placed at
(K MOD S) set, S = 2C = C
2
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19. A process which defines a series of tasks that have the
following four prtmary objectives is known
1. to identify all items that collectively define the software
conf iguration.
2. to manage changes to one or more of these items.
3. to facilitate the construction of differen versions of an
aPPlication.
4. to ensure that software quality is maintained as the
configuration evolves over time.
a) Software Quality Management Process
b) Software Configuration Management Process
c) Software Version Management process
d) Software Change Management process
Answer: (b)
Solution:
The goals of SCM(Software Configuration Mangaement) are
generally:
• Configuration identification
• Configuration control
• Configuration states accounting
• Configuration auditing
• Build management
• Process management
• Environment management
• Teamwork & Defect tracking
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20. The microinstructions stored in the control memory of a
processor have a width of 26 bits. Each microinstruction is
divided into three fields: a micro-operation field of 13 bits, a
next address field(X), and, a MUX select field(Y). There are 8
status bits in the inputs of the MUX.
How many bits are there in the X and y fields, and what is the
size of the control memory in number of words?
a) 10, 3, 1024
b) 8, 5, 256
c) 5, 8, 2048
d) 10, 3, 512
Answer: (a)
Solution:
Total size of micro instruction = 26 bits
Size of micro-operation = 13 bits
Total input for the multiplexer (status bits) input = 8
So the multiplexer selection lines field(Y) = 3 bits (23 = 8)
The number of bits in the next address field size(X) = 13 – 3
= 10 bits
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Size of control memorry =210 = 1024
Consider the following data path of a CPU
The, ALU, the bus and all the registers in the data path are of
identical size. All operations including instrumentation of the
PC and the GPRs are to be carried out in the ALU. Two clock
cycles are needed for memory read operation-the first one for
loading address in the MAR and the next one for loading data
from the memory but into the MDR.
21. Register renaming is done in pipelined processors
a) as an alternative to register allocation at compile time
b) for efficient access to function parameters and local
variables
c) to handle certain kinds of hazards
d) as part of address translation
Answer: (c)
Solution:
Register renaming is used for handling WAR and WAW
Hazards.
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22. Forward chaining systems are _ whereas backward chaining
systems are ____
a) Data driven, Data driven
b) Goal driven, Data driven
c) Data driven, Goal driven
d) Goal driven, Goal driven
Answer: (c)
Solution:
Because the data determine which rules are selected and used,
this method is called data-driven, in contrast to goal-driven
backword chaining interface. The forwarded chaining
approach is often employed by export systems.
23. A hard disk with a transfer rate of 10 Mbytes/second is
constantly transferring data to memory using DMA. The
processor runs at 600 MHz, and takes 300 and 900 clock
cycles to initiate and complete DMA transfer respectively. If
the size of the transfer is 20 Kbytes, what is the percentage of
processor time consumed for the transfer operation?
a) 5.0 %
b) 1.0 %
c) 0.5%
d) 0.1 %
Answer: (d)
Solution:
Transfer rare = 10k bytes/sec
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For 10K bytes it takes 1 msec
For 20K bit takes = 2 ms
CPU frequency is 600 MHZ,
T = 10−6 = 160ns
600
For initialize it takes 300 clk = 500ns (160 × 300)
For completing 900 clk = 1500 ns (160 × 900)
Total CPU time is 2000 ns = 2 s
Process consumes 2 s for each 2 msec.
∴1000th time in percentage it is 0.1%
24. The start and stop bits are used in serial communication for
a) error detection
b) error correction
c) synchronization
d) slowing down the communication
Answer: (c)
Solution:
During serial communication instead of a common
synchronization signal, the data stream contains
synchronization information in form of start signal prepares
the receiver for arrival of data and the stop signal resets its
states to enable triggering of a new sequence.
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25. Match the following :
List-l
A. Data couPling
B. Stamp couPling
C. Common couPling
D. Content couPling
List-ll
1. Module A and Module B have shared data
2. Dependency between modules is based on the fact they
communicate by only passing of data
3. When complete data structure is passed from one module to
another
4. When the control is passed from one module to the middle
of another
Codes:
AB C D
a) 3 2 1 4
b) 2 3 1 4
c) 2 3 4 1
d) 3 2 4 1
Answer: (b)
Solution:
Data coupling occurs when modules share data, for example
parameters.
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Stamp coupling occurs when module share a composite data
structure and use only part of it, possibly different parts
Common coupling occurs when two modules share same
global data.
Context coupling occurs when one module modifies or relies
on the internal working of another module.
26. Which of the following is not a form of memory?
a) Instruction cache
b) Instruction register
c) Instruction opcode
d) Translation look aside buffer
Answer: (c)
Solution:
Opcode is not a device.
27. Which of the following statement(s) is / are incorrect?
(i) Mapping the co-ordinates of the points and lines that iron
the picture into the appropriate co-ordinates on the device
or workstation is known as viewing transformation.
(ii) The right-handed Cartesian co-ordinates system in whose
co-ordinates we describe the picture is known as world
co-ordinate system.
(iii) The co-ordinate system that corresponds to the device or
workstation where the image is to be displayed is known
as physical device coordinate system.
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(iv) Left-handed co-ordinate system in which the display area
of the virtual display device corresponds to the unit (|x|)
square whose lower left-hand corner is at the origin of the
co-ordinate system is known as normalized device co-
ordinate system.
a) (i) only
b) (i) and (ii)
c) (iii) only
d) (iv) only
Answer: (d)
Solution:
NCS (Normalized coordinate system) is a right handed
coordinate system in which the displays area of the virtual
display device corresponding to unit (1 × 1) square whose
lower left hand corner is at the origin of the coordinate
system.
28. Consider the disk drive with the following specifications 16
surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector,
rotation speed 3000 rpm. The disk is operated in cycle stealing
mode whereby whenever one 4-byte word is ready it is sent to
memory; similarly, for writing, the disk interface reads a 4-
byte word from the memory in each DMA cycle. Memory
cycle time is 40 nsec. The maximum percentage of time that
the CPU gets blocked during DMA operation is
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a) 10
b) 25
c) 40
d) 50
Answer: (b)
Solution:
Disk rotation speed = 300rpm = 50rps
The data that can be read/write per track = 512 KB
The data that can be read/write in one second = 512 KB × 50
tracks
The time taken to read/write one byte data from disk/to the
disk = 1/(512KB × 50) = 38.14 nsec
Memorry cycle time = 40 n sec
During one DMA cycle 4 bytes of data is read from memorry.
Time taken to transfer the 4 bytes of data to the disk = 4 ×
38.14 = 152.56n sec.
The maximum % of time the CPU is blocked During DMA
cycle = 40n sec × 100/152.56 n sec = 26% ≅ 25%
29. Which of the forewing combination is preferred with respect
to cohesion and coupling?
a) low and low
b) low and high
c) high and low
d) high and high
Answer: (c)
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Solution:
Coupling is the degree of independence between software
modules; a measure of how closely connected two routines or
modules are; the strength of the relationship between modules.
Cohesion refers to the degree to which the elements of a
module belong together. Thus cohesion measures the strength
of relationship between pieces of functionality with a given
module.
All good software design will go for high cohesion and low
coupling
30. identify the addressing modes of below instructions and match
them:
List-I List-II
A. ADI 1. immediate addressing
B. STA 2. Direct addressing
C. CMA 3. implied addressing
D. SUB 4. Register addressing
Codes:
ABCD
a) 1 2 3 4
b) 2 1 4 3
c) 3 2 1 4
d) 4 3 2 1
Answer: (a)
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Solution:
ADI means add immediate, so it is immediate addressing.
STA means copy content of accumulator to the memory
location this is related with direct addressing
CMA means complement the content of accumulator. It’s
related with implied addressing
SUB is substation; it’s related with register addressing.
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